Re: [PATCH v3 2/5] drm/nouveau/gsp/r535: Add support for MEMSYS_GET_STATIC_CONFIG

[David Airlie]

On Wed, Sep 16, 2026 at 10:22 AM Lyude Paul <lyude@xxxxxxxxxx> wrote:
>
> This is a GSP structure describing various characteristics of the memory
> management system that GSP provides. Start by fetching it during driver
> load, but don't do anything with the information we get from it just yet.
>
> Signed-off-by: Lyude Paul <lyude@xxxxxxxxxx>
>
> ---
> V3
> * s/nvkm_gsp_rm_ctrl_get()/nvkm_gsp_rm_ctrl_rd()/
>
>  .../gpu/drm/nouveau/include/nvkm/subdev/gsp.h |  4 ++
>  .../drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c | 17 +++++++
>  .../nvkm/subdev/gsp/rm/r535/nvrm/gsp.h        | 45 +++++++++++++++++
>  .../drm/nouveau/nvkm/subdev/gsp/rm/r570/gsp.c |  8 +++
>  .../nvkm/subdev/gsp/rm/r570/nvrm/gsp.h        | 50 +++++++++++++++++++
>  .../gpu/drm/nouveau/nvkm/subdev/gsp/rm/rm.h   |  1 +
>  6 files changed, 125 insertions(+)
>
> diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h
> index 64fed208e4cf8..0e193baaf9bbb 100644
> --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h
> +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h
> @@ -156,6 +156,10 @@ struct nvkm_gsp {
>                 struct sg_table fbsr;
>         } sr;
>
> +       struct {
> +               bool use_raw_mode_comptagline_alloc;
> +       } memsys;
> +
>         struct {
>                 struct nvkm_gsp_mem mem;
>
> diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c
> index 09b17b85dc1ac..5df5365e744f5 100644
> --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c
> +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c
> @@ -1808,6 +1808,23 @@ r535_gsp_fini(struct nvkm_gsp *gsp, enum nvkm_suspend_state suspend)
>         return 0;
>  }
>
> +int
> +r535_gsp_get_static_memsys_info(struct nvkm_gsp *gsp)
> +{
> +       NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS *ctrl;
> +
> +       ctrl = nvkm_gsp_rm_ctrl_rd(&gsp->internal.device.subdevice,
> +                                   NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_STATIC_CONFIG,
> +                                   sizeof(*ctrl));
> +       if (IS_ERR(ctrl))
> +               return PTR_ERR(ctrl);
> +
> +       gsp->memsys.use_raw_mode_comptagline_alloc = ctrl->bUseRawModeComptaglineAllocation;
> +
> +       nvkm_gsp_rm_ctrl_done(&gsp->internal.device.subdevice, ctrl);
> +       return 0;
> +}
> +
>  int
>  r535_gsp_init(struct nvkm_gsp *gsp)
>  {
> diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/nvrm/gsp.h b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/nvrm/gsp.h
> index fd1170037c030..fee5418a72a68 100644
> --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/nvrm/gsp.h
> +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/nvrm/gsp.h
> @@ -789,6 +789,51 @@ typedef struct NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS {
>      NvBool bIsGCOFFSatisfied;
>  } NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS;
>
> +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS {
> +    /*! Determines if RM should use 1 to 1 Comptagline allocation policy */
> +    NvBool bOneToOneComptagLineAllocation;
> +
> +    /*! Determines if RM should use 1 to 4 Comptagline allocation policy */
> +    NvBool bUseOneToFourComptagLineAllocation;
> +
> +    /*! Determines if RM should use raw Comptagline allocation policy */
> +    NvBool bUseRawModeComptaglineAllocation;
> +
> +    /*! Has COMPBIT_BACKING_SIZE been overridden to zero (i.e. disabled)? */
> +    NvBool bDisableCompbitBacking;
> +
> +    /*! Determine if we need to disable post L2 compression */
> +    NvBool bDisablePostL2Compression;
> +
> +    /*! Is ECC DRAM feature supported? */
> +    NvBool bEnabledEccFBPA;
> +
> +    NvBool bL2PreFill;
> +
> +    /*! L2 cache size */
> +    NV_DECLARE_ALIGNED(NvU64 l2CacheSize, 8);
> +
> +    /*! Indicate whether fpba is present or not */
> +    NvBool bFbpaPresent;
> +
> +    /*! Size covered by one comptag */
> +    NvU32  comprPageSize;
> +
> +    /*! log32(comprPageSize) */
> +    NvU32  comprPageShift;
> +
> +    /*! RAM type */
> +    NvU32  ramType;
> +
> +    /*! LTC count */
> +    NvU32  ltcCount;
> +
> +    /*! LTS per LTC count */
> +    NvU32  ltsPerLtcCount;
> +} NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS;
> +
> +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_STATIC_CONFIG        (0x20800a1c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_MESSAGE_ID" */
> +
>  typedef union rpc_message_rpc_union_field_v03_00
>  {
>      NvU32      spare;
> diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/gsp.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/gsp.c
> index b45781cd0dfdc..5a51fe7e5ab98 100644
> --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/gsp.c
> +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/gsp.c
> @@ -137,6 +137,14 @@ r570_gsp_get_static_info(struct nvkm_gsp *gsp)
>                 }
>         }
>
> +       ret = r535_gsp_get_static_memsys_info(gsp);
> +       if (ret) {
> +               nvkm_error(&gsp->subdev, "Retrieving static memsys info failed\n");
> +               return ret;
> +       }
> +       nvkm_debug(&gsp->subdev, "memsys: Use raw mode for comptag allocations? %s\n",
> +                  str_yes_no(gsp->memsys.use_raw_mode_comptagline_alloc));
> +
>         return 0;
>  }
>
> diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/nvrm/gsp.h b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/nvrm/gsp.h
> index c458569af9d72..e2d9d1949e4e1 100644
> --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/nvrm/gsp.h
> +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/nvrm/gsp.h
> @@ -494,6 +494,56 @@ typedef struct
>
>  #define GSP_FW_WPR_META_REVISION  1
>
> +#define NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_MESSAGE_ID (0x1CU)
> +
> +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS {
> +    /*! Determines if RM should use 1 to 1 Comptagline allocation policy */
> +    NvBool bOneToOneComptagLineAllocation;
> +
> +    /*! Determines if RM should use 1 to 4 Comptagline allocation policy */
> +    NvBool bUseOneToFourComptagLineAllocation;
> +
> +    /*! Determines if RM should use raw Comptagline allocation policy */
> +    NvBool bUseRawModeComptaglineAllocation;
> +
> +    /*! Has COMPBIT_BACKING_SIZE been overridden to zero (i.e. disabled)? */
> +    NvBool bDisableCompbitBacking;
> +
> +    /*! Determine if we need to disable post L2 compression */
> +    NvBool bDisablePostL2Compression;
> +
> +    /*! Is ECC DRAM feature supported? */
> +    NvBool bEnabledEccFBPA;
> +
> +    NvBool bL2PreFill;
> +
> +    /*! L2 cache size */
> +    NV_DECLARE_ALIGNED(NvU64 l2CacheSize, 8);
> +
> +    /*! Indicate whether fpba is present or not */
> +    NvBool bFbpaPresent;
> +
> +    /*! Size covered by one comptag */
> +    NvU32  comprPageSize;
> +
> +    /*! log32(comprPageSize) */
> +    NvU32  comprPageShift;
> +
> +    /*! RAM type */
> +    NvU32  ramType;
> +
> +    /*! LTC count */
> +    NvU32  ltcCount;
> +
> +    /*! LTS per LTC count */
> +    NvU32  ltsPerLtcCount;
> +} NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS;
> +

Is this used anywhere? if the 535 and 570 structs match then don't include it.

Dave.