[PATCH v7 6/6] arm64: dts: broadcom: bcm2712: Add GPU IOMMU and IOMMU cache nodes
From: Daniel Drake via B4 Relay
Date: Sun Sep 27 2026 - 09:11:42 EST
From: Daniel Drake <dan@xxxxxxxxxxxxxxx>
Define the IOMMU and IOMMUC nodes for the Broadcom BCM2712 SoC found in
the Raspberry Pi 5. Enable use of the IOMMU for the HVS device
that handles memory allocations for the display block.
Signed-off-by: Daniel Drake <dan@xxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
index 45aa8ec5e2b1..aca9e0e3a874 100644
--- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
@@ -626,6 +626,19 @@ pcie2: pcie@1000120000 {
status = "disabled";
};
+ iommu4: iommu@1000005200 {
+ /* IOMMU for VC4 (HVS & MPL/TXP), Unicam, PISP-FE, MiniBVN */
+ compatible = "brcm,bcm2712-iommu";
+ reg = <0x10 0x5200 0x0 0x80>;
+ #iommu-cells = <0>;
+ brcm,iommu-cache = <&iommuc>;
+ };
+
+ iommuc: iommuc@1000005b00 {
+ compatible = "brcm,bcm2712-iommuc";
+ reg = <0x10 0x5b00 0x0 0x80>;
+ };
+
mip0: msi-controller@1000130000 {
compatible = "brcm,bcm2712-mip";
reg = <0x10 0x00130000 0x00 0xc0>,
@@ -701,5 +714,6 @@ hvs: hvs@107c580000 {
interrupt-parent = <&disp_intr>;
interrupts = <2>, <9>, <16>;
interrupt-names = "ch0-eof", "ch1-eof", "ch2-eof";
+ iommus = <&iommu4>;
};
};
--
2.55.0