[PATCH 03/15] perf/x86/intel: Reset active_pebs_data_cfg on CPU teardown

[Dapeng Mi]

cpuc->active_pebs_data_cfg tracks the PEBS data configuration currently
programmed into MSR_PEBS_DATA_CFG, and reprogramming is skipped when the
new value matches the cached one.

After a CPU offline/online cycle, MSR_PEBS_DATA_CFG may return to its
reset state, but active_pebs_data_cfg may still hold the pre-offline
value. If the next computed PEBS data configuration matches that stale
cache entry, the MSR update is incorrectly skipped, leaving
MSR_PEBS_DATA_CFG uninitialized for PEBS sampling and resulting in
incorrect PEBS records.

Clear active_pebs_data_cfg and MSR_PEBS_DATA_CFG during CPU teardown so
MSR_PEBS_DATA_CFG is always reprogrammed when the CPU comes back online.

Fixes: c22497f5838c ("perf/x86/intel: Support adaptive PEBS v4")
Signed-off-by: Dapeng Mi <dapeng1.mi@xxxxxxxxxxxxxxx>
---
 arch/x86/events/intel/core.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index b8dd7b73c31a..2f3eaf96daf5 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -6607,9 +6607,26 @@ static void fini_fixed_cntrs_on_cpu(int cpu)
 	wrmsrq_on_cpu(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
 }
 
+static void fini_adaptive_pebs_on_cpu(int cpu)
+{
+	struct cpu_hw_events *cpuc;
+
+	if (!x86_pmu.ds_pebs || !x86_pmu.intel_cap.pebs_baseline)
+		return;
+
+	/*
+	 * Clear active_pebs_data_cfg so MSR_PEBS_DATA_CFG can
+	 * be reprogrammed after CPU online.
+	 */
+	cpuc = &per_cpu(cpu_hw_events, cpu);
+	cpuc->active_pebs_data_cfg = 0;
+	wrmsrq_on_cpu(cpu, MSR_PEBS_DATA_CFG, 0);
+}
+
 static void intel_pmu_cpu_dying(int cpu)
 {
 	fini_fixed_cntrs_on_cpu(cpu);
+	fini_adaptive_pebs_on_cpu(cpu);
 	fini_debug_store_on_cpu(cpu);
 	fini_arch_pebs_on_cpu(cpu);
 }
-- 
2.34.1