[PATCH 05/15] perf/x86/intel: Pass correct PEBS counter mask to no-drain update path

[Dapeng Mi]

intel_pmu_drain_arch_pebs() calls intel_pmu_pebs_event_update_no_drain()
with X86_PMC_IDX_MAX, but that parameter is a counter bitmask, not a
max index value. As a result, PEBS event state is not updated/restored
correctly on the no-drain path.

Pass the PEBS counter mask to intel_pmu_pebs_event_update_no_drain().

Fixes: d21954c8a0ff ("perf/x86/intel: Process arch-PEBS records or record fragments")
Signed-off-by: Dapeng Mi <dapeng1.mi@xxxxxxxxxxxxxxx>
---
 arch/x86/events/intel/ds.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 8444670cee4a..0f24098587bf 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -3358,8 +3358,9 @@ static int intel_pmu_drain_arch_pebs(struct pt_regs *iregs,
 
 	rdmsrq(MSR_IA32_PEBS_INDEX, index.whole);
 
+	mask = hybrid(cpuc->pmu, arch_pebs_cap).counters & cpuc->pebs_enabled;
 	if (unlikely(!index.wr)) {
-		intel_pmu_pebs_event_update_no_drain(cpuc, X86_PMC_IDX_MAX);
+		intel_pmu_pebs_event_update_no_drain(cpuc, mask);
 		return 0;
 	}
 
@@ -3375,8 +3376,6 @@ static int intel_pmu_drain_arch_pebs(struct pt_regs *iregs,
 		index.thresh = ARCH_PEBS_THRESH_SINGLE;
 	wrmsrq(MSR_IA32_PEBS_INDEX, index.whole);
 
-	mask = hybrid(cpuc->pmu, arch_pebs_cap).counters & cpuc->pebs_enabled;
-
 	if (!iregs)
 		iregs = &dummy_iregs;
 
-- 
2.34.1