Re: [PATCH v2 0/9] soc: qcom: geni: Derive SE clock configuration from OPP table on SA8255P
From: Praveen Talari
Date: Mon Sep 28 2026 - 05:06:43 EST
Hi Konrad,
On 22-09-2026 18:36, Konrad Dybcio wrote:
On 9/11/26 7:33 PM, Praveen Talari wrote:
Hi Konrad,So I think the part that blocks going in the direction I
On 04-09-2026 14:30, Konrad Dybcio wrote:
On 9/4/26 9:56 AM, Ulf Hansson wrote:Currently, geni_se_clk_freq_match() relies on clk_perf_tbl to
On Tue, Sep 1, 2026 at 6:48 PM Praveen Talari[...]
<praveen.talari@xxxxxxxxxxxxxxxx> wrote:
So geni_se_clk_freq_match() is used by two consumer drivers today,The way I read it, isn't geni_se_clk_freq_match() more or less
drivers/spi/spi-geni-qcom.c and drivers/tty/serial/qcom_geni_serial.c.
Beyond the $subject series, there will be even more consumer drivers
that call these platform specific functions. As I said above, I don't
think this is moving things in the right direction.
If this can't be solved with generic frameworks (clocks and OPP),
please clarify why so we can figure out a better way forward.
dev_pm_opp_find_freq_exact() called in a loop with an increasing
divider?
determine the source clock index and divider corresponding to
a requested frequency.
suggested is that the index and divider values you mentioned
are then required to be fed into some GENI-internal registers:
-- drivers/spi/spi-geni-qcom.c
clk_sel = idx & CLK_SEL_MSK;
m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN;
writel(clk_sel, se->base + SE_GENI_CLK_SEL);
writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG);
and it seems like every protocol driver does some NIH things
to take care of that.. perhaps this bit could be moved up to
the common geni-se layer (Mukesh, are there some historical
reasons for this being handled in proto drivers?)
Just to confirm, would you like the clock programming logic to be moved into
the common GENI driver (geni-se.c)? If yes, I can take that up in a separate series.
Thanks,
Praveen Talari
I think this may just be an effect of how the hardware is wired
up - the ""DFS"" clocks that feed into the serial engines are
partly set up in the clock controller driver, but then there's
this bit:
-- drivers/clk/qcom/clk-rcg2.c
clk_rcg2_enable_dfs()
/*
* Rate changes with consumer writing a register in
* their own I/O region
*/
init->flags |= CLK_GET_RATE_NOCACHE;
init->ops = &clk_rcg2_dfs_ops;
which is the writes i mentioned above.
At a glance, plumbing this into OPP would require making GENI
SEs self-consumed clock providers, which sounds no less messy
Konrad