RE: [PATCH v2 2/3] spi: spi-nxp-fspi: enter stop mode before reconfiguring MCR0 and DLL

[Bough Chen (OSS)]

> -----Original Message-----
> From: Bough Chen (OSS) <haibo.chen@xxxxxxxxxxx>
> Sent: Thursday, September 24, 2026 6:25 PM
> To: Michael Walle <michael@xxxxxxxx>; Bough Chen (OSS)
> <haibo.chen@xxxxxxxxxxx>; Han Xu <han.xu@xxxxxxx>; Yogesh Gaur
> <yogeshgaur.83@xxxxxxxxx>; Mark Brown <broonie@xxxxxxxxxx>
> Cc: linux-spi@xxxxxxxxxxxxxxx; imx@xxxxxxxxxxxxxxx; linux-
> kernel@xxxxxxxxxxxxxxx; Bough Chen <haibo.chen@xxxxxxx>
> Subject: RE: [PATCH v2 2/3] spi: spi-nxp-fspi: enter stop mode before
> reconfiguring MCR0 and DLL
> 
> 
> > -----Original Message-----
> > From: Michael Walle <michael@xxxxxxxx>
> > Sent: Thursday, September 24, 2026 6:08 PM
> > To: Bough Chen (OSS) <haibo.chen@xxxxxxxxxxx>; Han Xu
> > <han.xu@xxxxxxx>; Yogesh Gaur <yogeshgaur.83@xxxxxxxxx>; Mark
> Brown
> > <broonie@xxxxxxxxxx>
> > Cc: linux-spi@xxxxxxxxxxxxxxx; imx@xxxxxxxxxxxxxxx; linux-
> > kernel@xxxxxxxxxxxxxxx; Bough Chen <haibo.chen@xxxxxxx>
> > Subject: Re: [PATCH v2 2/3] spi: spi-nxp-fspi: enter stop mode before
> > reconfiguring MCR0 and DLL
> >
> > On Tue Jul 28, 2026 at 12:18 PM CEST, haibo.chen wrote:
> > > From: Haibo Chen <haibo.chen@xxxxxxx>
> > >
> > > In nxp_fspi_select_mem() the RX sample clock source (MCR0[RXCLKSRC])
> > > and the DLL control registers (DLLxCR) are reconfigured while the
> > > FlexSPI module is still enabled. According to the FlexSPI reference
> > > manual initialization sequence, MCR0 and the DLL control registers
> > > should be programmed while the module is in stop mode, i.e. with
> > > MCR0[MDIS] set to 1, and the module re-enabled (MCR0[MDIS] = 0)
> > > afterwards.
> > >
> > > Wrap the RX sample clock source selection and the DLL calibration/
> > > override reconfiguration in a stop-mode window to align with the RM
> > > and avoid reconfiguring timing-critical registers while the module
> > > is active.
> > >
> > > Signed-off-by: Haibo Chen <haibo.chen@xxxxxxx>
> >
> > This will actually cause the following error on an i.MX 95 19x19 EVK
> > (imx95-19x19-evk.dts):
> >
> >   nxp-fspi 425e0000.spi: DLL lock failed, please fix it!
> >
> > Any ideas what causes this? I'm running the latest linux-next kernel.
> 
> Hi Michael, thanks for report this issue.
> 
> I can reproduce this issue on my side also, will look into it. I'll get back to you if
> I find anything.

Hi Michael,

I find the root cause. There are 2 issues here.

1, for the log:  nxp-fspi 425e0000.spi: DLL lock failed, please fix it!
    Yes, it is really involved by this patch, For DLL calibration, need to be done when module enable (MCR0[MDIS] = 0), otherwise, DLL will not lock.
    I will do more test on other platforms like imx8ulp/imx8m/imx91.  Will send one patch to fix it.

2. for the dump log: WARNING: drivers/spi/spi-nxp-fspi.c:1079 at nxp_fspi_exec_op+0xd88/0xe3c, CPU#1: kworker/u24:4/64
    After debug, I find even DLL do not lock in 8D-8D-8D mode, the first two command also done successfully, but the third command always trigger the WARN_ON(ret).
    Here is the command information when I dump the LUT.
[    1.887237] nxp-fspi 425e0000.spi: CMD[9f9f] lutval[0:879f879f 1:a700b310 2:00000000 3:00000000], size: 0x00000006
[    1.897633] nxp-fspi 425e0000.spi: CMD[505] lutval[0:87058705 1:a700b310 2:00000000 3:00000000], size: 0x00000002
[    1.907950] nxp-fspi 425e0000.spi: CMD[3535] lutval[0:87358735 1:a700b310 2:00000000 3:00000000], size: 0x00000002
   
CMD[9f9f] (RDID)、CMD[505] (RDSR) can be done normally，only CMD[3535] (RDSR2)  trigger the timeout.
the spi-nor on imx95-19x19-evk board is mt35xu512aba, and it do not support RDSR2. I add the following change then issue gone:

diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index f97f2dead8c2..35bf386bb66a 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -180,7 +180,8 @@ static int mt35xu512aba_post_sfdp_fixup(struct spi_nor *nor)
        nor->params->cmd_ext_type = SPI_NOR_EXT_REPEAT;
        nor->params->rdsr_dummy = 8;
        nor->params->rdsr_addr_nbytes = 0;
-
+
+       nor->params->opcodes.read_sr2 = 0;
        /*
         * The BFPT quad enable field is set to a reserved value so the quad
         * enable function is ignored by spi_nor_parse_bfpt(). Make sure we

This is involved by commit 63489002d397 ("mtd: spi-nor: Refactor Read Status/Write Status support"), seems not only micron-st is impacted, I will find a correct method and send patch to fix it.

Regards
Haibo Chen


> 
> Regards
> Haibo Chen
> >
> > -michael
> >
> > > ---
> > >  drivers/spi/spi-nxp-fspi.c | 14 ++++++++++++++
> > >  1 file changed, 14 insertions(+)
> > >
> > > diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
> > > index
> > >
> >
> 6de6d432cdcb2ee383a02d72f20000045903e176..a426b8d92193a4e303f4
> > 11cd17c1
> > > 6cb31c3f3873 100644
> > > --- a/drivers/spi/spi-nxp-fspi.c
> > > +++ b/drivers/spi/spi-nxp-fspi.c
> > > @@ -867,6 +867,7 @@ static void nxp_fspi_select_mem(struct nxp_fspi
> > > *f,
> > struct spi_device *spi,
> > >     unsigned long rate = op->max_freq;
> > >     int ret;
> > >     uint64_t size_kb;
> > > +   u32 reg;
> > >
> > >     /*
> > >      * Return when following condition all meet, @@ -896,6 +897,15
> > > @@ static void nxp_fspi_select_mem(struct nxp_fspi *f, struct
> > > spi_device *spi,
> > >
> > >     dev_dbg(f->dev, "Target device [CS:%x] selected\n",
> > > spi_get_chipselect(spi, 0));
> > >
> > > +   /*
> > > +    * Per the FlexSPI reference manual (initialization sequence), MCR0 and
> > > +    * the DLL control registers should be configured while the module is in
> > > +    * stop mode (MCR0[MDIS] = 1). Enter stop mode before
> > reconfiguring the
> > > +    * RX sample clock source and the DLL, then exit stop mode
> > afterwards.
> > > +    */
> > > +   reg = fspi_readl(f, f->iobase + FSPI_MCR0);
> > > +   fspi_writel(f, reg | FSPI_MCR0_MDIS, f->iobase + FSPI_MCR0);
> > > +
> > >     nxp_fspi_select_rx_sample_clk_source(f, op_is_dtr);
> > >     rate = min(f->max_rate, op->max_freq);
> > >
> > > @@ -928,6 +938,10 @@ static void nxp_fspi_select_mem(struct nxp_fspi
> > > *f,
> > struct spi_device *spi,
> > >     else
> > >             nxp_fspi_dll_override(f);
> > >
> > > +   /* Exit stop mode now that MCR0 and the DLL have been
> > reconfigured. */
> > > +   reg = fspi_readl(f, f->iobase + FSPI_MCR0);
> > > +   fspi_writel(f, reg & ~FSPI_MCR0_MDIS, f->iobase + FSPI_MCR0);
> > > +
> > >     f->pre_op_rate = op->max_freq;
> > >
> > >     f->selected = spi_get_chipselect(spi, 0);
>