[PATCH v2 07/15] PCI: rcar-gen4: Separate hardware setup from resource acquisition
From: Koichiro Den
Date: Mon Sep 28 2026 - 12:56:24 EST
Factor out the hardware setup needed by Root Port recovery into helpers.
Recovery needs to reset and restore the controller while keeping its
clocks enabled and the Gen5 PHY initialized.
- From rcar_gen4_pcie_common_init(), extract the power reset and mode
setup. Leave clock enabling and Application/Local reset control in
common_init(), so recovery can keep the APP registers accessible.
- From the V4H/V4M and Gen5 .init() callbacks, extract the SoC-specific
register setup. This allows recovery to restore those settings without
taking another clock or PHY initialization reference.
- From rcar_gen4_pcie_host_init(), extract the Root Port register setup
and PERST# release. Both paths need this host-specific sequence after
the per-SoC initialization or reset.
No functional changes.
Signed-off-by: Koichiro Den <den@xxxxxxxxxxxxx>
---
Changes in v2:
- Separate hardware setup extraction from the .reinit() addition.
- Keep the reset_control_status() check, so the power reset assertion
and the 1 ms wait after it remain conditional. (Marek)
drivers/pci/controller/dwc/pcie-rcar-gen4.c | 125 ++++++++++++--------
1 file changed, 77 insertions(+), 48 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
index 75e74fe3889d..e73ef6ccb145 100644
--- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
+++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
@@ -236,20 +236,13 @@ static void rcar_gen4_pcie_stop_link(struct dw_pcie *dw)
rcar->drvdata->ltssm_control(rcar, false);
}
-static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
+/* Clocks must be enabled and the Application/Local reset deasserted. */
+static int rcar_gen4_pcie_reset(struct rcar_gen4_pcie *rcar)
{
struct dw_pcie *dw = &rcar->dw;
u32 val;
int ret;
- ret = clk_bulk_prepare_enable(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
- if (ret) {
- dev_err(dw->dev, "Enabling core clocks failed\n");
- return ret;
- }
-
- reset_control_deassert(dw->core_rsts[DW_PCIE_CORE_RST].rstc);
-
if (!reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc)) {
reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
/*
@@ -268,8 +261,7 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
} else if (rcar->drvdata->mode == DW_PCIE_EP_TYPE) {
val |= DEVICE_TYPE_EP;
} else {
- ret = -EINVAL;
- goto err_unprepare;
+ return -EINVAL;
}
if (dw->num_lanes < 4)
@@ -279,7 +271,7 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
ret = reset_control_deassert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
if (ret)
- goto err_unprepare;
+ return ret;
/*
* Assure the reset is latched and the core is ready for DBI access.
@@ -295,6 +287,26 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
fsleep(1000);
return 0;
+}
+
+static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
+{
+ struct dw_pcie *dw = &rcar->dw;
+ int ret;
+
+ ret = clk_bulk_prepare_enable(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
+ if (ret) {
+ dev_err(dw->dev, "Enabling core clocks failed\n");
+ return ret;
+ }
+
+ reset_control_deassert(dw->core_rsts[DW_PCIE_CORE_RST].rstc);
+
+ ret = rcar_gen4_pcie_reset(rcar);
+ if (ret)
+ goto err_unprepare;
+
+ return 0;
err_unprepare:
reset_control_assert(dw->core_rsts[DW_PCIE_CORE_RST].rstc);
@@ -312,16 +324,10 @@ static void rcar_gen4_pcie_common_deinit(struct rcar_gen4_pcie *rcar)
clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
}
-static int rcar_gen4_v4h_v4m_pcie_init(struct rcar_gen4_pcie *rcar)
+static void rcar_gen4_v4h_v4m_pcie_configure(struct rcar_gen4_pcie *rcar)
{
struct dw_pcie *dw = &rcar->dw;
u32 val;
- int ret;
-
- /* R-Car Gen4 common initialization. */
- ret = rcar_gen4_pcie_common_init(rcar);
- if (ret)
- return ret;
/* R-Car V4H and V4M specific additional initialization. */
val = dw_pcie_readl_dbi(dw, PCIE_PORT_LANE_SKEW);
@@ -333,6 +339,17 @@ static int rcar_gen4_v4h_v4m_pcie_init(struct rcar_gen4_pcie *rcar)
val = readl(rcar->base + PCIEPWRMNGCTRL);
val |= APP_CLK_REQ_N | APP_CLK_PM_EN;
writel(val, rcar->base + PCIEPWRMNGCTRL);
+}
+
+static int rcar_gen4_v4h_v4m_pcie_init(struct rcar_gen4_pcie *rcar)
+{
+ int ret;
+
+ ret = rcar_gen4_pcie_common_init(rcar);
+ if (ret)
+ return ret;
+
+ rcar_gen4_v4h_v4m_pcie_configure(rcar);
return 0;
}
@@ -343,22 +360,11 @@ static void rcar_gen5_pcie_deinit(struct rcar_gen4_pcie *rcar)
rcar_gen4_pcie_common_deinit(rcar);
}
-static int rcar_gen5_pcie_init(struct rcar_gen4_pcie *rcar)
+static void rcar_gen5_pcie_configure(struct rcar_gen4_pcie *rcar)
{
struct dw_pcie *dw = &rcar->dw;
- int ret;
u32 val;
- /* R-Car Gen4 and Gen5 common initialization. */
- ret = rcar_gen4_pcie_common_init(rcar);
- if (ret)
- return ret;
-
- /* R-Car Gen5 specific additional initialization. */
- ret = phy_init(rcar->phy);
- if (ret)
- goto err_unprepare;
-
dw_pcie_dbi_ro_wr_en(dw);
val = dw_pcie_readl_dbi(dw, PCIE_PORT_LANE_SKEW);
@@ -377,13 +383,25 @@ static int rcar_gen5_pcie_init(struct rcar_gen4_pcie *rcar)
val |= APP_CLK_REQ_N | APP_CLK_PM_EN |
APP_READY_ENTR_L23 | APP_REQ_ENTR_L1;
writel(val, rcar->base + PCIEPWRMNGCTRL);
+}
- return 0;
+static int rcar_gen5_pcie_init(struct rcar_gen4_pcie *rcar)
+{
+ int ret;
-err_unprepare:
- rcar_gen4_pcie_common_deinit(rcar);
+ ret = rcar_gen4_pcie_common_init(rcar);
+ if (ret)
+ return ret;
- return ret;
+ ret = phy_init(rcar->phy);
+ if (ret) {
+ rcar_gen4_pcie_common_deinit(rcar);
+ return ret;
+ }
+
+ rcar_gen5_pcie_configure(rcar);
+
+ return 0;
}
static int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *rcar)
@@ -621,21 +639,11 @@ static void rcar_gen4_pcie_host_perst_assert(struct dw_pcie_rp *pp, bool assert)
}
/* Host mode */
-static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *pp)
+static int rcar_gen4_pcie_host_setup(struct dw_pcie_rp *pp)
{
struct dw_pcie *dw = to_dw_pcie_from_pp(pp);
- struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
int ret;
- if (pp->bridge)
- pp->bridge->enable_device = rcar_gen4_pcie_enable_device;
-
- rcar_gen4_pcie_host_perst_assert(pp, true);
-
- ret = rcar->drvdata->init(rcar);
- if (ret)
- return ret;
-
/*
* According to the section 3.5.7.2 "RC Mode" in DWC PCIe Dual Mode
* Rev.5.20a and 3.5.6.1 "RC mode" in DWC PCIe RC databook v5.20a, we
@@ -647,13 +655,34 @@ static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *pp)
ret = rcar_gen4_pcie_host_msi_init(pp);
if (ret)
- goto err;
+ return ret;
msleep(PCIE_T_PVPERL_MS); /* pe_rst requires 100msec delay */
-
rcar_gen4_pcie_host_perst_assert(pp, false);
return 0;
+}
+
+static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *pp)
+{
+ struct dw_pcie *dw = to_dw_pcie_from_pp(pp);
+ struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
+ int ret;
+
+ if (pp->bridge)
+ pp->bridge->enable_device = rcar_gen4_pcie_enable_device;
+
+ rcar_gen4_pcie_host_perst_assert(pp, true);
+
+ ret = rcar->drvdata->init(rcar);
+ if (ret)
+ return ret;
+
+ ret = rcar_gen4_pcie_host_setup(pp);
+ if (ret)
+ goto err;
+
+ return 0;
err:
rcar->drvdata->deinit(rcar);
--
2.51.0