Re: [PATCH 5/5] PCI/quirks: Avoid certain BAR 0 address with igb

[David Laight]

On Mon, 28 Sep 2026 17:30:41 +0300 (EEST)
Ilpo Järvinen <ilpo.jarvinen@xxxxxxxxxxxxxxx> wrote:

> On Mon, 28 Sep 2026, David Laight wrote:
> 
> > On Mon, 28 Sep 2026 15:20:13 +0300 (EEST)
> > Ilpo Järvinen <ilpo.jarvinen@xxxxxxxxxxxxxxx> wrote:
> >   
> > > On Thu, 24 Sep 2026, Bjorn Helgaas wrote:
> > >   
> > > > [+cc Rafael, ACPI resource question]
> > > > 
> > > > On Wed, Sep 23, 2026 at 04:17:55PM +0300, Ilpo Järvinen wrote:    
> > > > > While testing the resource placement changes, my tests hit a case where
> > > > > igb fails to probe when BAR 0 is placed at 0x9c000000:
> > > > > 
> > > > >    90000000-9cffffff : PCI Bus 0000:a0
> > > > >   -  90000000-902fffff : PCI Bus 0000:a1
> > > > >   -    90000000-900fffff : 0000:a1:00.0
> > > > >   -      90000000-900fffff : igb
> > > > >   -    90100000-901fffff : 0000:a1:00.0
> > > > >   -    90200000-90203fff : 0000:a1:00.0
> > > > >   -      90200000-90203fff : igb
> > > > >   +  9be00000-9c0fffff : PCI Bus 0000:a1  
> > 
> > Is that valid?
> > I'm no expect but I wouldn't expect an address range to cross a power of 2 boundary.  
> 
> Hi,
> 
> Bridge windows are defined by a base/limit pair, both with 1M granularity. 
> There's nothing that disallows a bridge window crossing a power of 2 
> boundary in the spec (AFAIK).
> 
> Note that after this quirk is applied reshuffling the device BAR 
> resources, the same crossing is still there and the device works.
> 
> Perhaps you mixed this up with BAR resources that indeed must to be 
> naturally aligned.
> 

I did say I wasn't an expert :-)
The PCIe book I've got is just over 20 years old (only 1000 pages).
I know rather more about the TLPs - we had a problem with some fpga logic
that didn't like getting two completions for a single read.

But it would be consistent with something 'not liking' BAR0 being at
9bxxxxxx and BAR1 at 9cxxxxxx.

David