[PATCH 2/2] arm64: dts: exynos850: Add operating points for CPUs and enable cpufreq
From: Alexey Klimov
Date: Mon Sep 28 2026 - 23:13:47 EST
Exynos850 has two clusters with four Cortex-A55 cores each. The OPPs are
identical for both clusters.
Add OPPs for both clusters and replace cpu clocks with ACPM
EXYNOS850_CLK_ACPM_DVFS_CPUCL{0,1} clocks.
The maximum nominal frequency should be 2.002 Ghz but at this point the
following OPP is not added here:
opp-2002000000 {
opp-hz = /bits/ 64 <2002000000>;
opp-microvolt = <1050000>;
clock-latency-ns = <500000>;
};
due to stability issues. Testing on a fully loaded system with CPU-bound
tasks triggers data aborts and illegal instruction errors at 2.002 GHz
after 1-2 hours of such stress testing.
Running the same workload overnight on a CPUs fixed at previous OPP didn't
lead to any issues so opp-1846000000 is currentlly the highest one as it is
considered safe.
Higher OPPs can be re-evaluated once thermal support is implemented.
Signed-off-by: Alexey Klimov <alexey.klimov@xxxxxxxxxx>
---
arch/arm64/boot/dts/exynos/exynos850.dtsi | 224 +++++++++++++++++++++++++++++-
1 file changed, 220 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi
index 91c6cee8f483..36501e5903f8 100644
--- a/arch/arm64/boot/dts/exynos/exynos850.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi
@@ -100,8 +100,9 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a55";
reg = <0x0>;
enable-method = "psci";
- clocks = <&cmu_cpucl0 CLK_CLUSTER0_SCLK>;
- clock-names = "cluster0_clk";
+ clocks = <&acpm_ipc EXYNOS850_CLK_ACPM_DVFS_CPUCL0>;
+ clock-names = "cpucl0";
+ operating-points-v2 = <&cpucl0_opp_table>;
};
cpu1: cpu@1 {
@@ -109,6 +110,8 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a55";
reg = <0x1>;
enable-method = "psci";
+ clocks = <&acpm_ipc EXYNOS850_CLK_ACPM_DVFS_CPUCL0>;
+ operating-points-v2 = <&cpucl0_opp_table>;
};
cpu2: cpu@2 {
@@ -116,6 +119,8 @@ cpu2: cpu@2 {
compatible = "arm,cortex-a55";
reg = <0x2>;
enable-method = "psci";
+ clocks = <&acpm_ipc EXYNOS850_CLK_ACPM_DVFS_CPUCL0>;
+ operating-points-v2 = <&cpucl0_opp_table>;
};
cpu3: cpu@3 {
@@ -123,6 +128,8 @@ cpu3: cpu@3 {
compatible = "arm,cortex-a55";
reg = <0x3>;
enable-method = "psci";
+ clocks = <&acpm_ipc EXYNOS850_CLK_ACPM_DVFS_CPUCL0>;
+ operating-points-v2 = <&cpucl0_opp_table>;
};
cpu4: cpu@100 {
@@ -130,8 +137,9 @@ cpu4: cpu@100 {
compatible = "arm,cortex-a55";
reg = <0x100>;
enable-method = "psci";
- clocks = <&cmu_cpucl1 CLK_CLUSTER1_SCLK>;
- clock-names = "cluster1_clk";
+ clocks = <&acpm_ipc EXYNOS850_CLK_ACPM_DVFS_CPUCL1>;
+ clock-names = "cpucl1";
+ operating-points-v2 = <&cpucl1_opp_table>;
};
cpu5: cpu@101 {
@@ -139,6 +147,8 @@ cpu5: cpu@101 {
compatible = "arm,cortex-a55";
reg = <0x101>;
enable-method = "psci";
+ clocks = <&acpm_ipc EXYNOS850_CLK_ACPM_DVFS_CPUCL1>;
+ operating-points-v2 = <&cpucl1_opp_table>;
};
cpu6: cpu@102 {
@@ -146,6 +156,8 @@ cpu6: cpu@102 {
compatible = "arm,cortex-a55";
reg = <0x102>;
enable-method = "psci";
+ clocks = <&acpm_ipc EXYNOS850_CLK_ACPM_DVFS_CPUCL1>;
+ operating-points-v2 = <&cpucl1_opp_table>;
};
cpu7: cpu@103 {
@@ -153,6 +165,210 @@ cpu7: cpu@103 {
compatible = "arm,cortex-a55";
reg = <0x103>;
enable-method = "psci";
+ clocks = <&acpm_ipc EXYNOS850_CLK_ACPM_DVFS_CPUCL1>;
+ operating-points-v2 = <&cpucl1_opp_table>;
+ };
+ };
+
+ cpucl0_opp_table: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-130000000 {
+ opp-hz = /bits/ 64 <130000000>;
+ opp-microvolt = <625000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-182000000 {
+ opp-hz = /bits/ 64 <182000000>;
+ opp-microvolt = <625000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-247000000 {
+ opp-hz = /bits/ 64 <247000000>;
+ opp-microvolt = <625000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-351000000 {
+ opp-hz = /bits/ 64 <351000000>;
+ opp-microvolt = <625000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-442000000 {
+ opp-hz = /bits/ 64 <442000000>;
+ opp-microvolt = <625000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-546000000 {
+ opp-hz = /bits/ 64 <546000000>;
+ opp-microvolt = <625000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ opp-microvolt = <625000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-806000000 {
+ opp-hz = /bits/ 64 <806000000>;
+ opp-microvolt = <656250>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-949000000 {
+ opp-hz = /bits/ 64 <949000000>;
+ opp-microvolt = <681250>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1053000000 {
+ opp-hz = /bits/ 64 <1053000000>;
+ opp-microvolt = <706250>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1157000000 {
+ opp-hz = /bits/ 64 <1157000000>;
+ opp-microvolt = <737500>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1300000000 {
+ opp-hz = /bits/ 64 <1300000000>;
+ opp-microvolt = <781250>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1456000000 {
+ opp-hz = /bits/ 64 <1456000000>;
+ opp-microvolt = <825000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1586000000 {
+ opp-hz = /bits/ 64 <1586000000>;
+ opp-microvolt = <875000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1742000000 {
+ opp-hz = /bits/ 64 <1742000000>;
+ opp-microvolt = <937500>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1846000000 {
+ opp-hz = /bits/ 64 <1846000000>;
+ opp-microvolt = <981250>;
+ clock-latency-ns = <500000>;
+ };
+ };
+
+ cpucl1_opp_table: opp-table-1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-130000000 {
+ opp-hz = /bits/ 64 <130000000>;
+ opp-microvolt = <625000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-182000000 {
+ opp-hz = /bits/ 64 <182000000>;
+ opp-microvolt = <625000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-247000000 {
+ opp-hz = /bits/ 64 <247000000>;
+ opp-microvolt = <625000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-351000000 {
+ opp-hz = /bits/ 64 <351000000>;
+ opp-microvolt = <625000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-442000000 {
+ opp-hz = /bits/ 64 <442000000>;
+ opp-microvolt = <625000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-546000000 {
+ opp-hz = /bits/ 64 <546000000>;
+ opp-microvolt = <625000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ opp-microvolt = <625000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-806000000 {
+ opp-hz = /bits/ 64 <806000000>;
+ opp-microvolt = <656250>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-949000000 {
+ opp-hz = /bits/ 64 <949000000>;
+ opp-microvolt = <681250>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1053000000 {
+ opp-hz = /bits/ 64 <1053000000>;
+ opp-microvolt = <706250>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1157000000 {
+ opp-hz = /bits/ 64 <1157000000>;
+ opp-microvolt = <737500>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1300000000 {
+ opp-hz = /bits/ 64 <1300000000>;
+ opp-microvolt = <781250>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1456000000 {
+ opp-hz = /bits/ 64 <1456000000>;
+ opp-microvolt = <825000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1586000000 {
+ opp-hz = /bits/ 64 <1586000000>;
+ opp-microvolt = <875000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1742000000 {
+ opp-hz = /bits/ 64 <1742000000>;
+ opp-microvolt = <937500>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1846000000 {
+ opp-hz = /bits/ 64 <1846000000>;
+ opp-microvolt = <981250>;
+ clock-latency-ns = <500000>;
};
};
--
2.51.0