Re: [PATCH v4 1/3] dt-bindings: edac: cdns,ddr-edac: add Cadence DDR EDAC binding

[Krzysztof Kozlowski]

On Mon, Sep 28, 2026 at 12:45:47PM +0200, Paul Louvel wrote:
> Add the Cadence EDAC DT binding.

Which is?

A nit, subject: drop second/last, redundant "binding". The
"dt-bindings" prefix is already stating that these are bindings.
See also:
https://elixir.bootlin.com/linux/v7.1-rc7/source/Documentation/devicetree/bindings/submitting-patches.rst#L23

> 
> Reviewed-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
> Signed-off-by: Paul Louvel (Schneider Electric) <paul.louvel@xxxxxxxxxxx>
> ---
>  .../devicetree/bindings/edac/cdns,ddr-edac.yaml    | 61 ++++++++++++++++++++++
>  MAINTAINERS                                        |  6 +++
>  2 files changed, 67 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml b/Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml
> new file mode 100644
> index 000000000000..098e69ff6297
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml
> @@ -0,0 +1,61 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/edac/cdns,ddr-edac.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Cadence DDR EDAC
> +
> +maintainers:
> +  - Paul Louvel <paul.louvel@xxxxxxxxxxx>
> +
> +description: >

Drop >

> +  The Cadence DDR supports DDR2 and DDR3 memory with or without ECC.
> +  The bootloader must configure ECC mode in the memory controller.
> +
> +  The memory controller supports SECDED (single bit error correction, double bit
> +  error detection). ECC scrubbing has to be done via software.
> +
> +properties:
> +  compatible:
> +    items:
> +      - const: renesas,r9a06g032-ddr-edac # RZ/N1D
> +      - const: cdns,ddr-edac

I doubt this can be used standalone, so I am not sure what is the
benefit of cnds compatible.

> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: DDR controller clock
> +      - description: APB internal bus clock
> +
> +  clock-names:
> +    items:
> +      - const: ddrc
> +      - const: pclk
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks
> +  - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/clock/r9a06g032-sysctrl.h>
> +
> +    edac: memory-controller@4000d000 {

Drop unused label

Best regards,
Krzysztof