[PATCH] arm64: dts: qcom: shikra: fix sdhc interrupts property
From: Arnd Bergmann
Date: Tue Sep 29 2026 - 07:08:13 EST
From: Arnd Bergmann <arnd@xxxxxxxx>
The gicv3 on this chip uses a 4-cell interrupt specifier, which
includes the affinity, but the newly added mmc node uses the
3-cell format:
arch/arm64/boot/dts/qcom/shikra.dtsi:4151.4-27: Warning (interrupts_property): /soc@0/mmc@4784000:#interrupt-cells: size is (24), expected multiple of 16
Add a zero affinity, same as for the other I/O devices on this chip.
Fixes: c8e3d40457f1 ("arm64: dts: qcom: shikra: Add SD Card support")
Signed-off-by: Arnd Bergmann <arnd@xxxxxxxx>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 9823c591b02b..1814ab33e236 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -1470,8 +1470,8 @@ sdhc_2: mmc@4784000 {
compatible = "qcom,shikra-sdhci", "qcom,sdhci-msm-v5";
reg = <0x0 0x04784000 0x0 0x1000>;
- interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "hc_irq",
"pwr_irq";
--
2.53.0