[PATCH 1/4] arm64: dts: renesas: r9a09g057: Add ADC node
From: Prabhakar
Date: Tue Sep 29 2026 - 08:49:10 EST
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Add the ADC device node to the RZ/V2H(P) SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 48 ++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index bbaab75681c2..d40d38c6a31c 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -608,6 +608,54 @@ wdt1: watchdog@14400000 {
status = "disabled";
};
+ adc: adc@11c00000 {
+ compatible = "renesas,r9a09g057-adc";
+ reg = <0 0x11c00000 0 0x400>;
+ interrupts = <GIC_SPI 918 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 919 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 920 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "adi", "gbadi", "gcadi",
+ "cmpai", "cmpbi";
+ clocks = <&cpg CPG_MOD 0x108>, <&cpg CPG_MOD 0x107>;
+ clock-names = "adclk", "pclk";
+ resets = <&cpg 0xf6>;
+ power-domains = <&cpg>;
+ dmas = <&dmac0 0x24c8>, <&dmac1 0x24c8>, <&dmac2 0x24c8>,
+ <&dmac3 0x24c8>, <&dmac4 0x24c8>;
+ dma-names = "rx", "rx", "rx", "rx", "rx";
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ };
+ channel@1 {
+ reg = <1>;
+ };
+ channel@2 {
+ reg = <2>;
+ };
+ channel@3 {
+ reg = <3>;
+ };
+ channel@4 {
+ reg = <4>;
+ };
+ channel@5 {
+ reg = <5>;
+ };
+ channel@6 {
+ reg = <6>;
+ };
+ channel@7 {
+ reg = <7>;
+ };
+ };
+
rtc: rtc@11c00800 {
compatible = "renesas,r9a09g057-rtca3", "renesas,rz-rtca3";
reg = <0 0x11c00800 0 0x400>;
--
2.55.0