Re: [PATCH v7 3/3] arm: dts: altera: add Draeger M48 CPU Module

[Petko Manolov]

On 26-09-28 09:18:03, Dinh Nguyen wrote:
> 
> According to all my documentations, the Cyclone5 SoCFPGA has 3 GPIO ports, and
> those are already mapped in the DTSI. The address space that you have
> specified here is for FPGA bridge. Which leads me to believe that this GPIO is
> in the FPGA.

You are correct.  These bindigs are some sort of leftover and Draeger folks
confirmed that they should be removed.

Sending out new patch series...


		Petko