[PATCH 4/5] sparc64: Derive VA masking support from the machine description

[Stian Halseth]

VA masking is not named in the cpu node's hwcap-list. The machine
description carries va-mask-nz-mask instead, which is present and
non-zero only on a chip that has the feature. A SPARC M7 reports
0x80808080.

Read that property rather than matching on sun4v_chip_type, so the
kernel does not have to carry a list of every chip that implements VA
masking.

hwcaps[] gains "vamask" as well, for firmware that does name it. The M7
does not.

The bit lands at 32, so a 32-bit task cannot see it: compat_binfmt_elf.c
narrows AT_HWCAP to Elf32_Addr.

Signed-off-by: Stian Halseth <stian@xxxxxx>
---
 arch/sparc/include/asm/elf_64.h |  1 +
 arch/sparc/kernel/setup_64.c    | 32 +++++++++++++++++++++++++++++++-
 2 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/arch/sparc/include/asm/elf_64.h b/arch/sparc/include/asm/elf_64.h
index 714ca79c88d7e..12832e1126d8a 100644
--- a/arch/sparc/include/asm/elf_64.h
+++ b/arch/sparc/include/asm/elf_64.h
@@ -106,6 +106,7 @@
 #define HWCAP_SPARC_PAUSE_NSEC	0x20000000 /* PAUSE has nanosecond granularity */
 #define HWCAP_SPARC_MWAIT	0x40000000 /* MWAIT available */
 #define HWCAP_SPARC_SPARC5	0x80000000 /* SPARC5 insns available */
+#define HWCAP_SPARC_VAMASK	0x100000000UL /* VA masking available */
 
 #define CORE_DUMP_USE_REGSET
 
diff --git a/arch/sparc/kernel/setup_64.c b/arch/sparc/kernel/setup_64.c
index 71d30b3bf276f..6f3b1d56a8c79 100644
--- a/arch/sparc/kernel/setup_64.c
+++ b/arch/sparc/kernel/setup_64.c
@@ -387,7 +387,7 @@ static const char *hwcaps[] = {
 	"mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2",
 	"ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau",
 	"ima", "cspare", "pause", "cbcond", NULL /*reserved for crypto */,
-	"adp", "vis3b", "pause-nsec", "mwait", "sparc5",
+	"adp", "vis3b", "pause-nsec", "mwait", "sparc5", "vamask",
 };
 
 static const char *crypto_hwcaps[] = {
@@ -521,6 +521,33 @@ static unsigned long __init mdesc_cpu_hwcap_list(void)
 	return caps;
 }
 
+/* VA masking is not named in the hwcap-list.  The cpu node describes it
+ * with va-mask-nz-mask instead, which is non-zero when the chip has it.
+ */
+static bool __init mdesc_cpu_has_vamask(void)
+{
+	struct mdesc_handle *hp;
+	const u64 *mask;
+	bool ret = false;
+	u64 pn;
+
+	hp = mdesc_grab();
+	if (!hp)
+		return false;
+
+	pn = mdesc_node_by_name(hp, MDESC_NODE_NULL, "cpu");
+	if (pn == MDESC_NODE_NULL)
+		goto out;
+
+	mask = mdesc_get_property(hp, pn, "va-mask-nz-mask", NULL);
+	if (mask && *mask)
+		ret = true;
+
+out:
+	mdesc_release(hp);
+	return ret;
+}
+
 /* This yields a mask that user programs can use to figure out what
  * instruction set this cpu supports.
  */
@@ -598,6 +625,9 @@ static void __init init_sparc64_elf_hwcap(void)
 					AV_SPARC_FMAF);
 		}
 	}
+	if (mdesc_cpu_has_vamask())
+		cap |= HWCAP_SPARC_VAMASK;
+
 	sparc64_elf_hwcap = cap | mdesc_caps;
 
 	report_hwcaps(sparc64_elf_hwcap);
-- 
2.43.0