Re: [PATCH v2 1/3] dt-bindings: clock: altr,agilex72-clkmgr: add Agilex72 clock manager

[Krzysztof Kozlowski]

On Tue, Sep 29, 2026 at 05:38:12PM +0800, evon.chiam@xxxxxxxxxx wrote:
> From: "Chiam, Evon" <evon.chiam@xxxxxxxxxx>
> 
> The Agilex72 clock manager exposes four register regions: the clock
> manager itself plus three general purpose PLLs.
> 
> Add the schema and the clock ID header that consumers index.
> 
> Signed-off-by: Chiam, Evon <evon.chiam@xxxxxxxxxx>
> ---

Where is patch 3/3?

> Changes in v2:
> - Subject: dropped the redundant "binding" suffix.
> - Reworded the commit message.
> - Dropped the external fixed-clock nodes from the example; they are not
>   relevant to this binding.
> - Dropped AGILEX72_NUM_CLKS from the clock ID header; it is not part of
>   the binding. The driver derives it instead.
> - Added the clocks and clock-names properties for the four external
>   reference clocks, made them required, and used them in the example.

...

> +  clocks:
> +    items:
> +      - description: External oscillator input
> +      - description: Internal oscillator divided by 2
> +      - description: Internal oscillator divided by 10
> +      - description: FPGA fabric to SoC free running clock
> +
> +  clock-names:
> +    items:
> +      - const: osc1

osc

> +      - const: cb-intosc-div2-clk

Drop -clk

> +      - const: cb-intosc-div10-clk

Names are odd, seems like you put here source clock names, not the
actual logical names of the inputs.

> +      - const: f2s-free-clk
> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - clocks
> +  - clock-names
> +  - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    clkmgr: clock-controller@915c000 {

and drop unused label.

Best regards,
Krzysztof