Re: [PATCH] RISC-V: errata: Add SiFive MAL-9092 workaround

[Paul Walmsley]

On Mon, 17 Aug 2026, Yong-Xuan Wang wrote:

> SiFive cores with MAL-9092 require fence.rw instructions around
> HLV/HLVX/HSV hypervisor instructions to ensure proper memory ordering
> when accessing guest memory.
> 
> Note that HSTATUS.HU is cleared during KVM initialization, restricting
> hypervisor instructions to HS-mode only. If future changes enable
> HSTATUS.HU for U-mode access, additional errata considerations will be
> needed.
> 
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@xxxxxxxxxx>
> Reviewed-by: Samuel Holland <samuel.holland@xxxxxxxxxx>

Thanks, queued for v7.3-rc.


- Paul