Re: [PATCH v2 2/2] spi: axi-spi-engine: fix stale SYNC IRQ pending in trigger_enable

[Nuno Sá]

On Wed, 2026-09-30 at 14:09 +0100, Mark Brown wrote:
> On Tue, Sep 29, 2026 at 11:17:45PM -0300, Jonathan Santos wrote:
> > spi_engine_trigger_enable() sends SYNC(1) and polls SYNC_ID, it never
> > clears the INT_PENDING[SYNC] bit afterward. This leaves a stale pending
> > interrupt that can fire spuriously when INT_SYNC is later enabled.
> 
> > +
> > +	/* Clear the stale SYNC pending bit so it doesn't fire when the IRQ is
> > later enabled */
> > +	writel_relaxed(SPI_ENGINE_INT_SYNC, spi_engine->base +
> > SPI_ENGINE_REG_INT_PENDING);
> > +
> >  	if (ret)
> >  		return ret;
> 
> I'm not seeing anything here for the issue with ensuring posted writes
> are completed before we drop the lock?  The write may not be visible on
> enother CPU, we need a read from the controller or something.

Just for my understanding, why would it be an issue? The trigger register seems to
only be accessible from the trigger callbacks which are protected by a lock where we
have implied barriers. Im sure I'm missing what can go wrong here :)

- Nuno Sá