[PATCH v2 0/3] soundwire: qcom: add multi-master support

From: Srinivas Kandagatla

Date: Thu Oct 01 2026 - 05:44:08 EST


This patch series adds support to the multi-master in existing soundwire
controller driver.

On Qualcomm Glymur SoC, both TX and RX soundwire controllers are wired
up in multi master mode connecting to an SDCA compliant Tambora codec.

One of the two controllers (tx,rx) act as primary controller in this
instance its tx which provides clock and control and some data lines and
other controller instance in this case rx act as dependent controller
providing extra data lanes to primary controller. This is called multi
master mode in Qualcomm Soundwire controller.

Multi Master mode allows synchronous transport across two independent
soundwire masters. This includes synchronized clock-stop, clock-resume,
clock scaling and bank switch between both masters, the Primary master
will ensure that.

>From the slave's point of view there is still one SoundWire bus with
one clock and one control lane; the extra DATA lanes just come from
a different pad on the SoC.

Currently the bindings are added in a way that its possible to add more
than one dependent, however to keep things simple the driver only
supports single dependent for now.

Topology (2+2 lane example):

Primary IP Dependent IP
+-----------------+ +-----------------+
| MM_SYNC <=====+=================+=====> MM_SYNC |
| | | |
| SWR_CLK ---+ | | |
| CTRL ---+ | | |
| DATA0 ---+ | | DATA0 ---+ |
| DATA1 ---+ | | DATA1 ---+ |
+--------------|--+ +------------|----+
| |
v v
+-----------+-----------+ +---------+---------+
| SWR_CLK, CTRL, | | bus DATA2, |
| bus DATA0, DATA1 | | DATA3 |
+-----------+-----------+ +---------+---------+
| |
+----------------+----------------+
|
v
+--------------+
| Slave |
+--------------+

Patch 1 adds two new DT properties qcom,multi-master-mode and
qcom,multi-master-peer for describing the pair.

Patch 2 wires up the primary and dependent roles in the driver.

Patch 3 programs SWRM_V3_MM_SYNC_CONFIG on both sides so their frame
generators lock to a single SWR_CLK.

Tested on Glymur (SC8480XP) CRD with WCD9378 in compute mode. HPH
playback and mic capture both work.

Changes in v2:
- Dependent-side safety: skip ctrl->intr_mask and CPU_EN writes on
the dependent
- Probe init order: run qcom_swrm_init() on the primary first, then
on the peer. The dependent's frame-gen poll cannot complete until
the primary (sole SWR_CLK provider in MM mode) has started the
clock.
- Peer teardown on probe failure and remove: disable peer SWRM
COMP_CFG + mask peer CPU IRQs so the peer releases the shared
SWR_CLK and devres can free the primary without a dangling
back-pointer.
- wake_irq request failure now routes to err_clk (was err_init,
which skipped the peer cross-link teardown and leaked hclk).
- qcom_swrm_remove deletes the sdw bus before clearing peer_ctrl;
in-flight bus ops dereference it.
- Re-program the dependent's MM_SYNC from the primary's
runtime_resume (dependent has no PM-runtime of its own).

v1: https://lore.kernel.org/all/cover.1789114385.git.srinivas.kandagatla@xxxxxxxxxxxxxxxx

Srinivas Kandagatla (3):
dt-bindings: soundwire: qcom: describe multi-master
soundwire: qcom: add multi-master support
soundwire: qcom: program MM_SYNC for multi-master

.../bindings/soundwire/qcom,soundwire.yaml | 108 +++++++-
drivers/soundwire/qcom.c | 261 ++++++++++++++++--
2 files changed, 341 insertions(+), 28 deletions(-)

--
2.53.0