[PATCH] sh: add SH7305 interrupt controller support

[Artem Novak]

Add interrupt controller support for the Renesas SH7305.

Describe the TMU interrupt vectors, interrupt mask registers and
interrupt register used by the SH7305, and register the controller
through the existing SuperH INTC framework.

Signed-off-by: Artem Novak <artem122novak@xxxxxxxxx>
---
 arch/sh/kernel/cpu/sh4a/Makefile      |  1 +
 arch/sh/kernel/cpu/sh4a/intc-sh7305.c | 85 +++++++++++++++++++++++++++
 2 files changed, 86 insertions(+)
 create mode 100644 arch/sh/kernel/cpu/sh4a/intc-sh7305.c

diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index baf73a8fc2a0..1e6cc301056a 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7770)	+= setup-sh7770.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7780)	+= setup-sh7780.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7785)	+= setup-sh7785.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7786)	+= setup-sh7786.o intc-shx3.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7305)	+= intc-sh7305.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7343)	+= setup-sh7343.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7722)	+= setup-sh7722.o serial-sh7722.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7723)	+= setup-sh7723.o
diff --git a/arch/sh/kernel/cpu/sh4a/intc-sh7305.c b/arch/sh/kernel/cpu/sh4a/intc-sh7305.c
new file mode 100644
index 000000000000..3b26d7ef0577
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/intc-sh7305.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas SH7305 interrupt controller support
+ *
+ * Copyright (C) 2026 Artem Novak
+ */
+
+#include <linux/init.h>
+#include <linux/sh_intc.h>
+
+enum {
+	UNUSED = 0,
+	ENABLED,
+	DISABLED,
+
+	TMU0_TUNI0,
+	TMU0_TUNI1,
+	TMU0_TUNI2,
+};
+
+/*
+ * SH7305 TMU interrupt event codes.
+ */
+static struct intc_vect vectors[] __initdata = {
+	INTC_VECT(TMU0_TUNI0, 0x400),
+	INTC_VECT(TMU0_TUNI1, 0x420),
+	INTC_VECT(TMU0_TUNI2, 0x440),
+};
+
+/*
+ * SH7305 IMR4 / IMCR4
+ *
+ * TMU0 channels occupy bits corresponding to TUNI0..2.
+ */
+static struct intc_mask_reg mask_registers[] __initdata = {
+	{
+		0xa4080090, 0xa40800d0, 8,
+		{
+			0,
+			TMU0_TUNI2,
+			TMU0_TUNI1,
+			TMU0_TUNI0,
+			0,
+			0,
+			0,
+			0,
+		}
+	},
+};
+
+/*
+ * SH7305 IPRA
+ *
+ * Four 4-bit interrupt priority fields:
+ *
+ *   bits 15..12  TMU0 channel 0
+ *   bits 11..8   TMU0 channel 1
+ *   bits  7..4   TMU0 channel 2
+ *   bits  3..0   unused here
+ */
+static struct intc_prio_reg prio_registers[] __initdata = {
+	{
+		0xa4080000, 0, 16, 4,
+		{
+			TMU0_TUNI0,
+			TMU0_TUNI1,
+			TMU0_TUNI2,
+			0,
+		}
+	},
+};
+
+static struct intc_desc intc_desc __initdata = {
+	.name		= "sh7305",
+	.force_enable	= ENABLED,
+	.force_disable	= DISABLED,
+
+	.hw = INTC_HW_DESC(vectors, NULL, mask_registers,
+			     prio_registers, NULL, NULL),
+};
+
+void __init plat_irq_setup(void)
+{
+	register_intc_controller(&intc_desc);
+}
-- 
2.55.0