[PATCH v2 4/5] ARM: dts: axis: artpec6: sort all properties
From: Henrik Grimler
Date: Fri Oct 02 2026 - 05:57:28 EST
To make as easy as possible to read devicetree nodes, the properties
should be alphabetical, with a few exceptions (compatible, reg,
status, ..). Update the ARTPEC-6 dtses to use preferred style. Issues
are detected by dt-check-style when run in strict mode as:
axis/artpec6.dtsi:93: [property-order] property 'compatible' out of canonical order (should sort before '#clock-cells')
Signed-off-by: Henrik Grimler <henrik.grimler@xxxxxxxx>
---
arch/arm/boot/dts/axis/artpec6-devboard.dts | 8 +++---
arch/arm/boot/dts/axis/artpec6.dtsi | 40 ++++++++++++++---------------
2 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/arch/arm/boot/dts/axis/artpec6-devboard.dts b/arch/arm/boot/dts/axis/artpec6-devboard.dts
index 042a9cc920c6..9a91f9758442 100644
--- a/arch/arm/boot/dts/axis/artpec6-devboard.dts
+++ b/arch/arm/boot/dts/axis/artpec6-devboard.dts
@@ -46,18 +46,18 @@ &pcie {
};
ðernet {
- status = "okay";
-
phy-handle = <&phy1>;
phy-mode = "gmii";
+ status = "okay";
+
mdio {
+ compatible = "snps,dwmac-mdio";
#address-cells = <0x1>;
#size-cells = <0x0>;
- compatible = "snps,dwmac-mdio";
phy1: phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
device_type = "ethernet-phy";
+ compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
};
};
diff --git a/arch/arm/boot/dts/axis/artpec6.dtsi b/arch/arm/boot/dts/axis/artpec6.dtsi
index 2f75a9df0963..6e69cde0a609 100644
--- a/arch/arm/boot/dts/axis/artpec6.dtsi
+++ b/arch/arm/boot/dts/axis/artpec6.dtsi
@@ -45,9 +45,9 @@
#include <dt-bindings/clock/axis,artpec6-clkctrl.h>
/ {
+ compatible = "axis,artpec6";
#address-cells = <1>;
#size-cells = <1>;
- compatible = "axis,artpec6";
interrupt-parent = <&intc>;
cpus {
@@ -89,21 +89,21 @@ scu@faf00000 {
/* Main external clock driving CPU and peripherals */
ext_clk: ext-clk {
- #clock-cells = <0>;
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <50000000>;
};
eth_phy_ref_clk: eth-phy-ref-clk {
- #clock-cells = <0>;
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <125000000>;
};
clkctrl: clkctrl@f8000000 {
- #clock-cells = <1>;
compatible = "axis,artpec6-clkctrl";
reg = <0xf8000000 0x48>;
+ #clock-cells = <1>;
clocks = <&ext_clk>;
clock-names = "sys_refclk";
};
@@ -124,26 +124,26 @@ timer@faf00600 {
};
intc: interrupt-controller@faf01000 {
- interrupt-controller;
compatible = "arm,cortex-a9-gic";
+ reg = <0xfaf01000 0x1000>, <0xfaf00100 0x0100>;
+ interrupt-controller;
#interrupt-cells = <3>;
- reg = < 0xfaf01000 0x1000 >, < 0xfaf00100 0x0100 >;
};
pl310: cache-controller@faf10000 {
compatible = "arm,pl310-cache";
+ reg = <0xfaf10000 0x1000>;
cache-unified;
cache-level = <2>;
- reg = <0xfaf10000 0x1000>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ prefetch-data = <1>;
+ prefetch-instr = <1>;
arm,data-latency = <1 1 1>;
arm,tag-latency = <1 1 1>;
arm,filter-ranges = <0x0 0x80000000>;
arm,double-linefill = <1>;
arm,double-linefill-incr = <0>;
arm,double-linefill-wrap = <0>;
- prefetch-data = <1>;
- prefetch-instr = <1>;
arm,prefetch-offset = <0>;
arm,prefetch-drop = <1>;
};
@@ -160,16 +160,16 @@ pmu {
* leave the unwanted node as disabled.
*/
pcie: pcie@f8050000 {
+ device_type = "pci";
compatible = "axis,artpec6-pcie", "snps,dw-pcie";
reg = <0xf8050000 0x2000>,
<0xf8040000 0x1000>,
<0xc0000000 0x2000>;
reg-names = "dbi", "phy", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
ranges = <0x81000000 0 0 0xc0002000 0 0x00010000>, /* downstream I/O */
<0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>; /* non-prefetchable */
+ #address-cells = <3>;
+ #size-cells = <2>;
num-lanes = <2>;
bus-range = <0x00 0xff>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
@@ -226,9 +226,9 @@ pinctrl_uart3: uart3grp {
amba@0 {
compatible = "simple-bus";
+ ranges;
#address-cells = <0x1>;
#size-cells = <0x1>;
- ranges;
dma-ranges;
crypto@f4264000 {
@@ -283,14 +283,14 @@ dma1: dma@f8019400 {
};
ethernet: ethernet@f8010000 {
- clock-names = "stmmaceth", "ptp_ref";
+ compatible = "snps,dwmac-4.10a", "snps,dwmac";
+ reg = <0xf8010000 0x4000>;
clocks = <&clkctrl ARTPEC6_CLK_ETH_ACLK>,
<&clkctrl ARTPEC6_CLK_PTP_REF>;
- compatible = "snps,dwmac-4.10a", "snps,dwmac";
+ clock-names = "stmmaceth", "ptp_ref";
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_lpi";
- reg = <0xf8010000 0x4000>;
snps,axi-config = <&stmmac_axi_setup>;
snps,mtl-rx-config = <&mtl_rx_setup>;
@@ -333,8 +333,8 @@ uart0: serial@f8036000 {
clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
<&clkctrl ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
- pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
+ pinctrl-names = "default";
dmas = <&dma0 4 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>,
<&dma0 5 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>;
dma-names = "rx", "tx";
@@ -347,8 +347,8 @@ uart1: serial@f8037000 {
clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
<&clkctrl ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
- pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
+ pinctrl-names = "default";
dmas = <&dma0 6 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>,
<&dma0 7 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>;
dma-names = "rx", "tx";
@@ -361,8 +361,8 @@ uart2: serial@f8038000 {
clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
<&clkctrl ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
- pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
+ pinctrl-names = "default";
dmas = <&dma1 0 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>,
<&dma1 1 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>;
dma-names = "rx", "tx";
@@ -375,8 +375,8 @@ uart3: serial@f8039000 {
clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
<&clkctrl ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
- pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
+ pinctrl-names = "default";
dmas = <&dma1 2 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>,
<&dma1 3 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>;
dma-names = "rx", "tx";
--
2.43.0