[PATCH 1/2] clk: qcom: gcc-ipq5018: drop CLK_SET_RATE_PARENT from ubi0_axi_clk_src

[Andrei-Alexandru Bleortu]

ubi0_axi_clk_src has CLK_SET_RATE_PARENT, but its parents are XO and
the read-only GPLL0 and GPLL2 post-dividers, so propagating a rate
request can never change their rate.

It does make the clock core treat any rounding gap as a GPLL0 rate
change. Requesting 400 MHz (GPLL0 / 2) while GPLL0 reads back as
799999998 Hz makes GPLL0 the top of the change, and clk_change_rate()
then re-runs set_rate on every GPLL0 consumer. That includes the live
NoC clocks and sdcc1_apps_clk_src, which is gated at that moment and
fails with "rcg didn't update its configuration", leaving the eMMC
controller and the board hung.

Drop the flag so that a rate request on ubi0_axi_clk_src stays local to
it. gcc_ubi0_axi_clk keeps its flag and still forwards requests to this
clock.

Fixes: e3fdbef1bab8 ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018")

Assisted-by: LLM
Signed-off-by: Andrei-Alexandru Bleortu <me@xxxxxxxxxxxx>
---
 drivers/clk/qcom/gcc-ipq5018.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c
index add6a53d4df5..620b9ed72138 100644
--- a/drivers/clk/qcom/gcc-ipq5018.c
+++ b/drivers/clk/qcom/gcc-ipq5018.c
@@ -1197,7 +1197,6 @@ static struct clk_rcg2 ubi0_axi_clk_src = {
 		.parent_data = gcc_xo_gpll0_gpll2,
 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
 		.ops = &clk_rcg2_ops,
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
-- 
2.47.3