Re: [PATCH v2 1/4] dt-bindings: mmc: amlogic,meson-gx-mmc: document the T7 pipeline clock
From: Lucas Tanure
Date: Sat Oct 03 2026 - 04:14:56 EST
On 16/09/2026 21:37, Rob Herring wrote:
On Sat, Sep 05, 2026 at 04:32:31PM +0100, Lucas Tanure wrote:Yes, the SD controller doesn't work with this clock, so I don't think is a ABI break, as the current code doesn't work and the board crashes a lot.
The SD/eMMC controllers of the T7 SoC are physically far from the
NIC_MATRIX bus fabric, so the hardware design inserts a pipeline stage
in the middle of the bus path to help timing closure. This stage is fed
by its own gate clock and, when that clock is disabled, a controller
that starts a DMA transfer can never complete it.
Allow a fourth clock entry, named "pipeline", and require it for the
amlogic,t7-mmc compatible. The other controllers of this family keep
the existing three clocks.
Did the SD controller not work without this clock? If it did, then this
is an ABI break which is evident by the current warning in linux-next.
Rob
And a few patches got merged from my work, so I will resubmit a new series for this.
Thanks
Lucas