Re: [PATCH v5 0/8] clk: sunxi-ng: Add support for Allwinner A733 CCU and PRCM

[Junhui Liu]

Hi Chen-Yu,

On Sat Oct 3, 2026 at 9:37 PM CST, Chen-Yu Tsai wrote:
> On Wed, Sep 30, 2026 at 1:27 AM Junhui Liu <junhui.liu@xxxxxxxxxxxxx> wrote:
>>
>> Add support for the main CCU and the PRCM module (R-CCU) found in the
>> Allwinner A733 SoC. The clock architecture is derived from the previous
>> A523 design, with the MCU_CCU removed and the clock tree extended for
>> the additional functional blocks found on the A733.
>>
>> The A733 introduces a "pll-ref" clock that normalizes the physical
>> oscillator frequency, which can be 19.2MHz, 24MHz, or 26MHz, into a
>> consistent 24MHz reference for the PLL clock tree.
>>
>> The peripheral, video, and DE PLLs provide multiple independently gated
>> outputs with programmable dividers. Model these outputs as separate
>> divider-and-gate child clocks. Also follow the documented hierarchy for
>> the derived peripheral PLL outputs. The explicitly named PLL_AUDIO1 /2
>> and /5 outputs are modeled as fixed-factor clocks, with their divider
>> fields initialized accordingly.
>>
>> Also extend the sunxi-ng SDM (Sigma-Delta Modulation) support for the
>> dual-pattern register layout used by the A733 PLLs. PLL_AUDIO0 uses the
>> dual-pattern SDM support to synthesize its fractional output.
>> PLL_AUDIO1 does not expose fractional rates, but its SDM controls are
>> modeled so that stale settings left by firmware can be disabled when an
>> integer rate is programmed.
>
> Some of the clock controls, like the PLL and AHB/APB bus dividers, are
> secure by default and need to be set to non-secure for Linux to be able
> to use them properly. And there is also a TWD clock in the PRCM that the
> user manual says is secure only.
>
> Have you given any thought to this? If we end up having to convert to
> SCMI or something to handle those clocks it's going to be a bit ugly.
>
> And presumably things work now because the secure/non-secure access bit
> isn't in effect right now because you aren't using secure boot? At least
> this was a thing in the past...
>

Thanks for pointing this out. This is indeed something I had not
considered before. I will try enabling secure boot on my spare Cubie A7Z
board and test it on actual hardware.

For the PLL and AHB/APB bus clock controls, the user manual indicates
that the relevant security bits can be set by TF-A to allow the kernel
to access these registers. This also appears to be how this has
traditionally been handled on sunxi platforms. So I think we can do the
same in TF-A for the A733.

For bus_r_twd_clk, I will test whether the register is indeed always
secure. If it is, I think the clock can be removed from the kernel and
left enabled by its hardware reset value or by the boot firmware.

>
> Thanks
> ChenYu
>

-- 
Best regards,
Junhui Liu