Re: [PATCH v5 8/8] clk: sunxi-ng: a733: Add reset lines

[Chen-Yu Tsai]

On Tue, Sep 29, 2026 at 7:28 PM Junhui Liu <junhui.liu@xxxxxxxxxxxxx> wrote:
>
> Add the reset lines for the Allwinner A733 SoC. These reset control bits
> are integrated into the Bus Gate Reset (BGR) registers, typically
> sharing the same register address with their corresponding bus clock
> gates. Integrate them into the main CCU driver using the existing
> sunxi-ng ccu_reset framework, allowing the CCU to also function as a
> reset controller for the SoC.
>
> Tested-by: Jerome Brunet <jbrunet@xxxxxxxxxxxx>
> Reviewed-by: Andre Przywara <andre.przywara@xxxxxxx>
> Signed-off-by: Junhui Liu <junhui.liu@xxxxxxxxxxxxx>

Reviewed-by: Chen-Yu Tsai <wens@xxxxxxxxxx>