Re: [PATCH v3 1/2] wifi: rtw88: sdio: Fix unhandled RX request interrupt storm

[Luka Gejak]

October 5, 2026 at 05:35, "Ping-Ke Shih" <pkshih@xxxxxxxxxxx mailto:pkshih@xxxxxxxxxxx?to=%22Ping-Ke%20Shih%22%20%3Cpkshih%40realtek.com%3E > wrote:


> 
> Alastair D'Silva <alastair@xxxxxxxxxxx> wrote:
> 
> > 
> > 8051 and 3081 SDIO chipsets handle the REG_SDIO_HISR_RX_REQUEST status bit
> >  differently:
> >  
> >  - 8051-based chips (e.g. RTL8723BS, RTL8723CS, RTL8723DS):
> >  The hardware automatically clears REG_SDIO_HISR_RX_REQUEST once the RX
> >  buffer is empty. Software must not clear this bit, because the drain
> >  loop in rtw_sdio_rx_isr() re-reads REG_SDIO_HISR across iterations to
> >  decide whether more requests are pending. Clearing it in software
> >  terminates the loop after a single request, stranding the remainder of
> >  the FIFO. Additionally, RTL8723BS requires RTW_SDIO_HISR_CLEAR_MASK to
> >  avoid undefined bits causing resume storms.
> >  
> >  - 3081-based chips (e.g. RTL8821CS, RTL8822CS):
> >  The hardware does not automatically clear REG_SDIO_HISR_RX_REQUEST when
> >  the RX buffer is empty. Masking this bit out in software before writing
> >  back to HISR prevented it from ever being acknowledged in hardware,
> >  trapping the CPU core in an infinite interrupt storm loop that starved
> >  RCU and locked up the system. Furthermore, on 3081 chips the physical
> >  RX FIFO capacity is at most 24 KB (16 KB on RTL8821CS, 24 KB on
> >  RTL8822CS), which is well within the 64 KB loop budget.
> >  
> >  As the number of architecture-specific special cases has grown (16-bit vs
> >  32-bit register widths, differing HISR writeback timing, synthetic loop
> >  flags, and RTL8723BS resume masking), attempting to accommodate both
> >  architectures within a single monolithic handler has become fragile and
> >  prone to cross-architecture regressions.
> >  
> >  Resolve this by making rtw_sdio_handle_interrupt() a dispatcher with
> >  separate paths for 8051 and 3081:
> >  
> >  1. 8051 chips preserve the existing unmasked writeback behavior, leaving
> >  REG_SDIO_HISR_RX_REQUEST for hardware to drop and respecting
> >  RTW_SDIO_HISR_CLEAR_MASK on RTL8723BS.
> >  2. 3081 chips adopt the interrupt masking pattern: disable HIMR,
> >  acknowledge pending status bits in HISR via W1C, service the pending
> >  events, and re-enable HIMR. Any packet arriving during servicing
> >  latches REG_SDIO_HISR_RX_REQUEST in hardware and re-asserts the IRQ line
> >  once unmasked.
> >  
> >  Splitting into separate handlers isolates these quirks cleanly and
> >  simplifies future maintenance.
> >  
> >  Fixes: 65371a3f14e7 ("wifi: rtw88: sdio: Add HCI implementation for SDIO based chipsets")
> > 
> At this moment, did it support 3081-seris already?
> I feel this tag is too serious. 
> 
> > 
> > Cc: stable@xxxxxxxxxxxxxxx
> >  Assisted-by: LLM
> >  Signed-off-by: Alastair D'Silva <alastair@xxxxxxxxxxx>
> > 
> Acked-by: Ping-Ke Shih <pkshih@xxxxxxxxxxx>
>

Hi Ping-Ke,
I think you missed my review at [1].

Best regards,
Luka Gejak

[1]:https://lore.kernel.org/all/20261001060213.24759-1-luka.gejak@xxxxxxxxx/