[PATCH 0/5] spi: Add support for panic mem writes

[Paul Cercueil]

Hi,

This patchset updates the MTD spi-nor code as well as the spi-mem code
to add support for panic mem writes to a memory partition configured as
pstore.

In the context of a kernel panic, preemption, SMP and IRQs are disabled.
Therefore the SPI driver must make sure that its code paths don't sleep,
or rely on interrupts.

A driver that will respect these conditions can say so by setting the
'panic_write' flag in its spi_controller_mem_caps. The MTD core won't
attempt a panic mem write without this flag set.

Only the .exec_op() path will be used for panic writes, given that the
fallback code relies on the generic SPI API, which explicitly states
that it mustn't be called from code that can't sleep.

In case of a kernel panic with a compatible SPI driver, and a mem write
is attempted, the 'spi_mem_op' struct will have its 'panic_write' flag
set, and the SPI driver can then handle it accordingly.

The spi-cadence-xspi driver gets updated in the process, adding support
for a irq-less mode where register polling is used, so that it can
support panic mem writes.

Cheers,
-Paul

Tanmay Jagdale (5):
  spi: spi-mem: Add support for panic mem writes
  mtd: spi-nor: Add support for panic writes
  spi: cadence-xspi: Add irq-less support
  spi: cadence-xspi: Don't use infinite timeout in register poll
  spi: cadence-xspi: Add support for panic writes

 drivers/mtd/spi-nor/core.c     |  67 ++++++++++++++++++++-
 drivers/spi/spi-cadence-xspi.c | 103 ++++++++++++++++++++-------------
 drivers/spi/spi-mem.c          |  25 ++++++++
 include/linux/spi/spi-mem.h    |   5 ++
 4 files changed, 156 insertions(+), 44 deletions(-)

-- 
2.47.3