Re: [PATCH v3 1/2] EDAC/amd64: Mask UMC chip select to the four implemented selects

[Borislav Petkov]

On Fri, Oct 02, 2026 at 05:02:03PM +0530, Vishal Badole wrote:
> For DRAM ECC errors, the chip select value can be found in the
> MCA_SYND[ErrorInformation] field.
> 
> ErrorInformation[2:0] was first documented in Zen1. The 3 bit field
> implied that up to 8 chip selects may be used.
> 
> However, all Zen-based systems have only ever had up to 4 chip selects.
> So only bits [1:0] would contain a valid chip select value.
> 
> Future systems are redefining the field to ErrorInformation[1:0]. This
> matches the existing 'up to 4 chip selects' implementations. And it
> frees up the extra bit for other decoding.
> 
> Change the current chip select mask from 0x7 to 0x3 to prepare for the
> decode change.
> 
> Fixes: 713ad54675fd ("EDAC, amd64: Define and register UMC error decode function")
> Cc: <stable@xxxxxxxxxxxxxxx>
> Suggested-by: Yazen Ghannam <yazen.ghannam@xxxxxxx>
> Signed-off-by: Vishal Badole <Vishal.Badole@xxxxxxx>
> Reviewed-by: Yazen Ghannam <yazen.ghannam@xxxxxxx>
> ---
>  drivers/edac/amd64_edac.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Applied, thanks.

-- 
Regards/Gruss,
    Boris.

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