Re: [PATCH v6 3/3] phy: nuvoton: phy-ma35d1-usb2: extend to dual-port with OTG support

[Joey Lu]

Vinod Koul 於 2026/10/5 下午 06:07 寫道:
> On 29-09-26, 10:08, Joey Lu wrote:
> > PHY0 and PHY1 use the same power-on/reset sequence in USBPMISCR, with
> > PHY1 control bits shifted 16 positions relative to PHY0.  A separate
> > driver for PHY1 would duplicate this logic, so the existing driver is
> > extended to manage both ports.
> >
> > The original driver polled only DEVCKSTB after releasing PHY0 from
> > reset.  When USB0 operates in host mode (USB ID pin floating or tied
> > high) only HSTCKSTB and CK12MSTB assert; DEVCKSTB never sets.  Polling
> > exclusively for DEVCKSTB in host mode causes a 1 ms timeout on every
> > phy_init() call from the EHCI driver.  The init callback is changed to
> > accept either host-mode or device-mode clock stability, whichever
> > asserts first.
> >
> > The power_on and power_off callbacks are replaced by a single init
> > callback that handles PHY reset and clock-stable polling, because
> > there is no PHY-specific clock gate on MA35D1; the PHY analog block
> > derives its reference from the HXT crystal.
> >
> > A read-only USB role switch is registered for PHY0 to expose the USB0
> > role to userspace via the standard role-switch sysfs interface.  The
> > .set callback returns -EOPNOTSUPP because the hardware mux is fully
> > automatic with no software override path.  When CONFIG_USB_ROLE_SWITCH
> > is not enabled, the registration returns -ENODEV and the driver skips
> > the role switch gracefully without failing probe.
> >
> > Two new optional device-tree properties are implemented:
> >    - nuvoton,rcalcode: writes per-port 4-bit resistor calibration trim
> >      codes to the RCALCODE field in USBPMISCR.
> >    - nuvoton,oc-active-high: sets the UHOVRCURH bit in MISCFCR0 to treat
> >      the over-current detect input as active-high.
> >
> > Signed-off-by: Joey Lu <a0987203069@xxxxxxxxx>
> > ---
> >   drivers/phy/nuvoton/phy-ma35d1-usb2.c | 286 +++++++++++++++++++-------
> >   1 file changed, 211 insertions(+), 75 deletions(-)
> >
> > diff --git a/drivers/phy/nuvoton/phy-ma35d1-usb2.c b/drivers/phy/nuvoton/phy-ma35d1-usb2.c
> > index 9a459b700ed4..547c7d55d8ff 100644
> > --- a/drivers/phy/nuvoton/phy-ma35d1-usb2.c
> > +++ b/drivers/phy/nuvoton/phy-ma35d1-usb2.c
> > @@ -1,11 +1,16 @@
> >   // SPDX-License-Identifier: GPL-2.0
> >   /*
> > - * Copyright (C) 2024 Nuvoton Technology Corp.
> > + * Nuvoton MA35D1 USB 2.0 PHY driver
> > + *
> > + * Supports PHY0 (USB0 OTG port, shared between DWC2 gadget and EHCI0/OHCI0)
> > + * and PHY1 (USB1 host-only port, used by EHCI1/OHCI1). The hardware mux on
> > + * PHY0 switches automatically via the USB ID pin.
> > + *
> > + * Copyright (C) 2026 Nuvoton Technology Corp.
> Not correct, this should be updated to 2024-2026, you dont drop the
> copyright notices, you update them!
Agreed, will fix in v7 to preserve the original 2024 date and reflect 
this series' changes.
> >    */
> >   #include <linux/bitfield.h>
> >   #include <linux/clk.h>
> >   #include <linux/delay.h>
> > -#include <linux/io.h>
> why is this dropped?
This driver never did direct MMIO access (no readl()/writel()/ioremap()/
__iomem), even before this series - all register access goes through
regmap via syscon_regmap_lookup_by_phandle(). So linux/io.h was an
unused include already, and it's dropped here as part of the broader
rewrite touching this include block. Happy to keep it if you'd prefer
not to bundle unrelated include cleanup into this series.

Thanks for the review.

BR,
Joey