Re: [PATCH v6 0/8] riscv: optimize mode switch latency for Vector

[Paul Walmsley]

On Fri, 18 Sep 2026, Andy Chiu wrote:

> This series provide several optimizations targeting system call latency
> regarding vector context management. Before the series, the kernel
> handled user's vector context in an conservative way, where registers
> were null out and VS is tracked as DIRTY. This introduce excess context
> saving and restoring when there is a context swicth.  Also, the kernel
> turned off Vector at the exception entry, making all in-kernel vector
> usecase take the serialization cost, which includes context switch and
> user copies. The cost is not easy to hide as vector code are usually sit
> right after enabling V.
> 
> Since vector register are set to a known state at syscall exit, the
> series set VS to INIT at syscall entry and null out the vector register
> at the exit, skipping unnecessary saves and restores. The series also
> introduce riscv_novstateopt, when unset, enables vector in the kernel
> mode, and do not perform register nulling on the syscall fast path,
> where there is no context switch or kernel-mode vector during the
> syscall.
> 
> With the whole series, nginx request throughput vs base on a four-core
> Ascalon-S, by served page size (* = statistically distinct):
> 
>        86B     1KB     2KB     4KB     8KB     16KB    32KB
>   v5   +0.79%* +1.36%* +2.33%* +2.02%* +0.14%  +0.93%  +2.42%*
>   v6   +0.33%* -0.23%  +2.88%* +2.19%* +1.02%  +1.14%  +1.40%*
> 
> This series depends on [1], which is now queued in the KVM RISC-V tree
> [2]. For those who prefer git, the series is also available at [3].

Thanks.  Given the KVM fixes dependency, it's probably best to wait to 
merge most of these until v7.5.  But I think it's OK to pick up 1, 2, and 
3?  Will queue those for v7.4.


- Paul