Re: [PATCH v2] clk: qcom: mmcc-sdm660: enable the parents of the pixel clock sources

[Alexey Minnekhanov]

On 02.10.2026 19:46, Fabricio Akio via B4 Relay wrote:
> From: Fabricio Akio <fabricioakio@xxxxxxxxx>
>
> pclk0_clk_src and pclk1_clk_src are fed by the DSI PHY PLLs, which
> dsi_pll_14nm_vco_set_rate() resets and only clk_prepare() restarts. The
> DSI host sets the link rates before it prepares the PLL, so the RCG is
> updated against a stopped source, and if it is enabled at that point
> the update times out:
>
>    pclk0_clk_src: rcg didn't update its configuration.
>
> Seen on a board whose simple-framebuffer node lists the pixel clock:
> the RCG then reads enabled at msm's first modeset.
>
> Set CLK_OPS_PARENT_ENABLE on both so the core prepares the PLL around
> the rate change, as dispcc-sm8250 does for its pixel clock sources since
> commit acf7a91d0b0e ("clk: qcom: dispcc-sm8250: Enable parents for pixel
> clocks").
>
> Fixes: 5db3ae8b33de ("clk: qcom: Add SDM660 Multimedia Clock Controller (MMCC) driver")
> Signed-off-by: Fabricio Akio <fabricioakio@xxxxxxxxx>
> ---
> Changes in v2:
> - Set the flag on pclk1_clk_src as well, as Dmitry asked. v1 left it
>    out because this board has nothing on DSI1 to test it with.
> - Link to v1: https://patch.msgid.link/20261002-sdm660-pclk0-parent-enable-v1-1-d6ff889144e4@xxxxxxxxx
> ---
>   drivers/clk/qcom/mmcc-sdm660.c | 6 ++++--
>   1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/qcom/mmcc-sdm660.c b/drivers/clk/qcom/mmcc-sdm660.c
> index 9f8b8e29fa0f..827741229dd7 100644
> --- a/drivers/clk/qcom/mmcc-sdm660.c
> +++ b/drivers/clk/qcom/mmcc-sdm660.c
> @@ -984,7 +984,8 @@ static struct clk_rcg2 pclk0_clk_src = {
>   		.parent_data = mmcc_xo_dsi0pll_dsi1pll,
>   		.num_parents = ARRAY_SIZE(mmcc_xo_dsi0pll_dsi1pll),
>   		.ops = &clk_pixel_ops,
> -		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
> +		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE |
> +			 CLK_OPS_PARENT_ENABLE,
>   	},
>   };
>   
> @@ -998,7 +999,8 @@ static struct clk_rcg2 pclk1_clk_src = {
>   		.parent_data = mmcc_xo_dsi0pll_dsi1pll,
>   		.num_parents = ARRAY_SIZE(mmcc_xo_dsi0pll_dsi1pll),
>   		.ops = &clk_pixel_ops,
> -		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
> +		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE |
> +			 CLK_OPS_PARENT_ENABLE,
>   	},
>   };
>   
>
> ---
>
> Best regards,
>
> Fabricio Akio <fabricioakio@xxxxxxxxx>

I've verified that it at least doesn't break booting on 3 different
devices based on 3 different related SoCs:

 * sdm630-sony-pioneer (Xperia XA2)
 * sdm636-xiaomi-whyred (Redmi Note 5/Pro)
 * sdm660-xiaomi-lavender (Redmi Note 7)

I've also never seen before the warning about pclk0_clk_src not
updating its configuration. MMCC seemed to always work fine, but
given some recent fixes to clock drivers I'd be not surprised if
something was missed in initial porting..

Tested-by: Alexey Minnekhanov <alexeymin@xxxxxxxxxx>

--
Regards,
Alexey Minnekhanov