Re: [PATCH] i2c: designware: size the RX FIFO threshold to the queued transfer

[Navon John Lukose]

On Sun, Oct 04, 2026 at 11:12:22AM +0300, Andy Shevchenko wrote:
> I think you might need to adjust the commit message (and pick Mika's tag).
> My concern was the oddity behind /dev/cpu_dma_latency: Does the commit
> message suggest to set it like this (then it's no go)? Or does it state
> the fact that CPU power states affect the latency (then it should be
> clarified)? Or something else behind that?

The second. Fewer interrupts per transfer let the CPU idle between them,
which is where the power saving comes from, and the added latency is the
exit latency from those idle states. Holding cpu_dma_latency at 0 was only
how I measured that. v2 drops it from the commit message, gives the
latency figure and its cause below the cut, and picks up Mika's tag:

https://lore.kernel.org/all/20261007191911.502428-1-navonjohnlukose@xxxxxxxxx/