[PATCH v6 05/11] arm64: dts: qcom: ipq5210: Add C3 CPU idle state

From: Varadarajan Narayanan

Date: Thu Oct 08 2026 - 05:16:26 EST


Add the PSCI-backed C3 idle state for the Cortex-A53 CPUs and wire it to
all CPU nodes.

Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/ipq5210.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi
index 3183182d1cc7..331589a9c1ff 100644
--- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi
@@ -36,6 +36,7 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
+ cpu-idle-states = <&cpu_sleep_0>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
@@ -47,6 +48,7 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a53";
reg = <0x1>;
enable-method = "psci";
+ cpu-idle-states = <&cpu_sleep_0>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
@@ -58,6 +60,7 @@ cpu2: cpu@2 {
compatible = "arm,cortex-a53";
reg = <0x2>;
enable-method = "psci";
+ cpu-idle-states = <&cpu_sleep_0>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
@@ -69,6 +72,7 @@ cpu3: cpu@3 {
compatible = "arm,cortex-a53";
reg = <0x3>;
enable-method = "psci";
+ cpu-idle-states = <&cpu_sleep_0>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
@@ -80,6 +84,20 @@ l2_0: l2-cache {
cache-level = <2>;
cache-unified;
};
+
+ idle-states {
+ entry-method = "psci";
+
+ cpu_sleep_0: cpu-sleep-c3 { /* C3 */
+ compatible = "arm,idle-state";
+ idle-state-name = "power-down";
+ arm,psci-suspend-param = <0x40000003>;
+ entry-latency-us = <181>;
+ exit-latency-us = <149>;
+ min-residency-us = <703>;
+ local-timer-stop;
+ };
+ };
};

firmware {

--
2.34.1