RE: [RFC/DISCUSSION] x86/tsc: Handling legacy PIT fallback calibration on modern platforms

[Hahn, Matthias]

Dear Ping Jiang

Thx for following up. 

> I was reproducing this on i5-14600KF. My PIT delay wass ~13000 cycles, resulting in TSC calibration with 30 ppm error, tested by running `sudo dmesg | grep TSC` on host and VM.
>
> I wonder why I can't reproduce it.
> My motherboard is 'B760M-PLUS WIFI II'.

Did you by chance select "IO fabric low latency" in FW (BIOS) config or TCC mode which would include that knob? Then it's expected that you see lower latencies for PIT and you might not be able to reproduce (sorry I didn't mention). 

Regards,
Matthias

--
Dr. Matthias Hahn
Intel Deutschland GmbH
Phone: +49 (0)89 9914-3865
Mobile: +49 (0)173 6514578

-----Original Message-----
From: Ping K. Jiang <jiang_kangping@xxxxxxxxxxx> 
Sent: Wednesday, October 7, 2026 5:51 PM
To: Hahn, Matthias <matthias.hahn@xxxxxxxxx>; linux-kernel@xxxxxxxxxxxxxxx; x86@xxxxxxxxxx
Cc: tglx@xxxxxxxxxxxxx; mingo@xxxxxxxxxx; bp@xxxxxxxxx; dave.hansen@xxxxxxxxxxxxxxx; peterz@xxxxxxxxxxxxx
Subject: Re: [RFC/DISCUSSION] x86/tsc: Handling legacy PIT fallback calibration on modern platforms

 > We have recently observed an issue regarding TSC calibration fallback on  > modern client/server platforms (Specifically Raptor Lake and newer) when  > running inside restricted virtualized environments.
 >
 > On modern platforms, however, legacy port I/O cycle latency has increased  > substantially. In benchmark comparisons between older platforms (e.g.
 > Broadwell-DE) and modern silicon (Raptor Lake), 1024 PIT reads took ~2.7M  > cycles on BDX compared to ~21.3M cycles on RPL (~8x-10x slower, yielding  > ~10-20 us per read).
 >

Dear Dr. Hahn,

I was reproducing this on i5-14600KF. My PIT delay wass ~13000 cycles, resulting in TSC calibration with 30 ppm error, tested by running `sudo dmesg | grep TSC` on host and VM.

I wonder why I can't reproduce it.
My motherboard is 'B760M-PLUS WIFI II'.

Thanks!
Ping Jiang
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