[PATCH v6 00/15] Add basic clocks and resets for JHB100 SoC

[Changhuang Liang]

The JHB100 SoC includes CRG (Clock and Reset Generator) for multiple
subsystems:

The JHB100 SoC is divided into multiple subsystems, and basically
each subsystem includes a CRG(Clock and Reset Generator):
 - sys0crg/sys1crg/sys2crg/
 - per0crg/per1crg/per2crg/per3crg/
 - voutcrg
 - vcecrg
 - gpu0crg/gpu1crg
 - cpucrg
 - usbcrg
 - host0crg/host1crg
 - pcierpcrg
 - husb0crg/husb1crg
 - husbcmncrg
 - husbd0crg/husbd1crg
 - npucrg

In the current series, we will only add the following CRG:
 - sys0crg/sys1crg/sys2crg/
 - per0crg/per1crg/per2crg/per3crg/

The remaining CRG will be implemented in future series.

changes since v5:
- Remove the bindings related patch.

patch 4 (in v6):
- jh71x0_crg_probe(): report invalid parent indices with
  dev_err_probe() instead of returning a bare -EINVAL, so the failing
  clock name and index are visible in the log.
- Add #include <linux/property.h>.

patch 8 (in v6):
- Change the JH71X0_CLK_FRAC_MAX condition check to an else if.

patch 5/6/7/10/11/12/13 (in v6):
- Document the CLK_IS_CRITICAL and CLK_IGNORE_UNUSED policies.

v5: https://lore.kernel.org/all/20260930124317.5648-1-changhuang.liang@xxxxxxxxxxxxxxxx/
v4: https://lore.kernel.org/all/20260920120044.194901-1-changhuang.liang@xxxxxxxxxxxxxxxx/
v3: https://lore.kernel.org/all/20260807112923.191627-1-changhuang.liang@xxxxxxxxxxxxxxxx/
v2: https://lore.kernel.org/all/20260508053632.818548-1-changhuang.liang@xxxxxxxxxxxxxxxx/
v1: https://lore.kernel.org/all/20260402105523.447523-1-changhuang.liang@xxxxxxxxxxxxxxxx/

Changhuang Liang (15):
  clk: starfive: jh7110-sys: Fix memory leak in reset controller
    register
  clk: starfive: jh71x0: Move reset controller registration to jh71x0
    common code
  reset: starfive: jh7110: Match auxiliary device names to jh71x0 clk
    driver
  clk: starfive: jh71x0: Add generic CRG probe helper
  clk: starfive: Add JHB100 System-0 clock generator driver
  clk: starfive: Add JHB100 System-1 clock generator driver
  clk: starfive: Add JHB100 System-2 clock generator driver
  clk: starfive: Introduce idiv ops for inverted divider clocks
  clk: starfive: Expand the storage of clock parent index
  clk: starfive: Add StarFive JHB100 Peripheral-0 clock driver
  clk: starfive: Add StarFive JHB100 Peripheral-1 clock driver
  clk: starfive: Add StarFive JHB100 Peripheral-2 clock driver
  clk: starfive: Add StarFive JHB100 Peripheral-3 clock driver
  reset: starfive: jh71x0: Support discontiguous reset IDs
  reset: starfive: Add StarFive JHB100 reset driver

 MAINTAINERS                                   |  13 +
 drivers/clk/starfive/Kconfig                  |  72 +-
 drivers/clk/starfive/Makefile                 |   8 +
 .../clk/starfive/clk-starfive-jh7110-aon.c    |   2 +-
 .../clk/starfive/clk-starfive-jh7110-isp.c    |   2 +-
 .../clk/starfive/clk-starfive-jh7110-stg.c    |   2 +-
 .../clk/starfive/clk-starfive-jh7110-sys.c    |  57 +-
 .../clk/starfive/clk-starfive-jh7110-vout.c   |   2 +-
 drivers/clk/starfive/clk-starfive-jh7110.h    |   4 -
 drivers/clk/starfive/clk-starfive-jh71x0.c    | 165 ++++-
 drivers/clk/starfive/clk-starfive-jh71x0.h    |  24 +-
 .../clk/starfive/clk-starfive-jhb100-per0.c   | 617 ++++++++++++++++++
 .../clk/starfive/clk-starfive-jhb100-per1.c   | 162 +++++
 .../clk/starfive/clk-starfive-jhb100-per2.c   | 182 ++++++
 .../clk/starfive/clk-starfive-jhb100-per3.c   | 140 ++++
 .../clk/starfive/clk-starfive-jhb100-sys0.c   | 156 +++++
 .../clk/starfive/clk-starfive-jhb100-sys1.c   | 118 ++++
 .../clk/starfive/clk-starfive-jhb100-sys2.c   | 135 ++++
 drivers/reset/starfive/Kconfig                |   9 +
 drivers/reset/starfive/Makefile               |   1 +
 .../reset/starfive/reset-starfive-jh7110.c    |  10 +-
 .../reset/starfive/reset-starfive-jh71x0.c    |  99 ++-
 .../reset/starfive/reset-starfive-jh71x0.h    |  19 +
 .../reset/starfive/reset-starfive-jhb100.c    | 303 +++++++++
 24 files changed, 2216 insertions(+), 86 deletions(-)
 create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per0.c
 create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per1.c
 create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per2.c
 create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per3.c
 create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys0.c
 create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys1.c
 create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys2.c
 create mode 100644 drivers/reset/starfive/reset-starfive-jhb100.c

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2.25.1