Re: [PATCH 1/3] dt-bindings: iio: adc: add bindings for stm32 mdf filter
From: Olivier MOYSAN
Date: Thu Oct 08 2026 - 12:37:42 EST
Hi Conor,
On 10/8/26 12:11, Conor Dooley wrote:
On Wed, Oct 07, 2026 at 11:01:28AM +0200, Olivier MOYSAN wrote:
Hi Conor,
Thanks for the review
On 10/1/26 20:32, Conor Dooley wrote:
On Thu, Oct 01, 2026 at 04:56:45PM +0200, Olivier Moysan wrote:
Add bindings that describes STM32 MDF settings to support
digital filtering for Pulse Density Modulation (PDM) microphones
and analog sigma delta modulators.
Signed-off-by: Olivier Moysan <olivier.moysan@xxxxxxxxxxx>
---
.../bindings/iio/adc/st,stm32-mdf-adc.yaml | 383 ++++++++++++++++++
1 file changed, 383 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/st,stm32-mdf-adc.yaml
diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-mdf-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-mdf-adc.yaml
new file mode 100644
index 000000000000..f2fbc3e150e8
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-mdf-adc.yaml
@@ -0,0 +1,383 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/st,stm32-mdf-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32 Multi-function Digital Filter (MDF) ADC
+
+maintainers:
+ - Olivier Moysan <olivier.moysan@xxxxxxxxxxx>
+
+description: |
+ STM32 MDF ADC is a sigma delta analog-to-digital converter dedicated to
+ interface external sigma delta modulators to STM32 micro controllers.
+
+properties:
+ compatible:
+ enum:
+ - st,stm32mp25-mdf
+ - st,stm32mp23-mdf
+
+ reg:
+ minItems: 1
+ maxItems: 2
This needs an items list here. The size of the regions seems like crap
to begin with...
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ description: Internal clock used for MDF digital processing.
+ items:
+ - const: ker_ck
This is pointless when you only have one.
I agree that it could be dropped. However, it is useful for using
devm_regmap_init_mmio_clk.
Ah, because that function if you pass NULL to it, it doesn't mean no
string, it means no clock.
The MDF has two clocks (AHB clock for register accesses and ker_ck for peripheral processing). However, these two clocks share the same gate. So, only the ker_ck clock is exposed in the driver.
The regmap api is a convenient way to manage registers and gate the AHB clock only on register accesses. Removing clock-names no longer allows you to benefit from clock management handled by the regmap framework, and means that this must be managed explicitly, partially or entirely, in the driver.
+
+ "#clock-cells":
+ enum: [0, 1]
Why is this not fixed? Also why are parts of your own device consuming
the clocks?
Reading the docs, this has to be 1, you have two clocks?
Not sure why you skipped this and skipped explaining why you are
consuming your own clocks.
Yes, we can have two clocks gated independently but sharing the same rate.
Using the clock framework apis seemed to me the right way to manage cck1 and cck0 gating and divider computing. I think I would have to introduce proprietary properties and have to implement code in the driver, that would be handled natively by the framework otherwise.
+ clock-output-names:
+ description: |
+ CCK0 and CCK1 are optional output clocks, which share the same clock frequency,
+ but can be gated independently to save power.
+ minItems: 1
+ maxItems: 2
+ oneOf:
+ - items:
+ - const: cck0
+ - items:
+ - const: cck1
+ - items:
+ - const: cck0
+ - const: cck1
+
+ clock-frequency:
+ description: |
+ Common clock frequency (Hz) for CCK0 and CCK1 output clocks.
+ The frequency must be a multiple of the "ker_ck" clock frequency.
+ maximum: 25000000
Should not be needed, the consumers request what they need.
The CCKx clock frequency depends on the maximum rate supported by the sigma
delta converters (for instance a digital mic) and the expected decimation
ratio on the bitstream. Typically this determines the frequency on the SPI
bus.
This rate is defined statically and shared by the CCKx clocks. So IMHO, as
this rate is unique, it can look strange to let the consumer define it.
Moreover, it seems to me that clock-frequency is already used to configure
the frequency of a provider in some other bindings.
For instance: Documentation/devicetree/bindings/clock/silabs,si570.yaml
This is a binding from the age of antiquity, using it to justify your
use is actually harming your argument rather than helping. Your clock
consumers should be providing the information about what the rate should
be, and if you need to do this in dt you can use assigned-clock-rates.
ok, I will move this to clock consumer with assigned-clock properties.
So, it's not clear for me, what is the restriction on clock-frequency
property.
+
+ ranges: true
+
+ clock-ranges: true
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: mdf
Same applies here as to the clock names fwiw.
Yes, I removed this.
+
+ access-controllers:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ Phandle to the rifsc device to check access right.
+
+ power-domains:
+ maxItems: 1
+
+ st,interleave:
+ description: |
+ List of phandles of interleaved filters. The indexes of interleaved filters must be
+ consecutives starting from 0 (i.e in range [0..N]). The samples from interleaved filters
+ are muxed in a single channel and retrieved through the device associated to the filter 0.
+ The filters 1..N have to be enabled, but inherit their configuration from filter 0.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
No idea what these even are, but this is probably not the right way to
represent the relationship between devices. They're apparently ADCs, but
this is also an ADC so I'm not sure what's going on here at all.
Yeah, after more thought this should not be done like this at all,
especially if these filters the phandle point to are part of this device
itself, which I suspect they are. If that's the case, you don't need
phandles to even do this, you just need an int that says what N is.
Yes, can be an index as it is an internal reference. I will change this.
+
+required:
+ - compatible
+ - reg
+ - ranges
+ - clocks
+ - clock-names
+ - clock-ranges
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties: false
+
+patternProperties:
+ "^sitf@[0-9]+$":
+ type: object
+ description: Serial interface child node
Why is this a child node at all?
Probably not worth reviewing more without a link to the docs for this
device so I can figure out what on earth is going on!
The MDF is a digital filter for sigma-delta bitstreams, rather than the
analog-to-digital converter itself.
Here is the link to STM32MP25 reference manuel
https://www.st.com/resource/en/reference_manual/rm0457-stm32mp2325xx-advanced-armbased-3264bit-mpus-stmicroelectronics.pdf
Chapter 45: Multi-function digital filter (MDF)
On STMP32MP25 SoC, the MDF provides 8 serial interfaces (SITF) and 8 digital
filters (DFLT) which can be connected through a multiplexer.
Below is a schematic view of typical applications targeted by this
peripheral
Audio use case:
mdf
+-------------------------------------+
+------+ | +------+ +------+ +------+ |
| dmic | -> | | sitf | -> | mux | -> | dflt | -- | -> audio device
+------+ | +------+ +------+ +------+ |
+-------------------------------------+
For instance, in an audio use case the serial interface can be configured to
provide the clock to the digital microphone (cck0, cck1 or both) at a common
predefined rate, and to retrieve the PDM samples.
The serial interface provides this samples to a digital filter, which
delivers PCM samples on its output.
Analog use case:
mdf
+-------------------------------------+
+--------+ | +------+ +------+ +------+ |
| sd adc | -> | | sitf | -> | mux | -> | dflt | -- | -> iio device
+--------+ | +------+ +------+ +------+ |
+-------------------------------------+
So, looking at the docs and a brief chat with Jonathan about this
device, I believe you've got things backwards and this is actually the backend,
and the adc should be the one populating the io-backends property
pointing to this device. You should have io-backend-cells, and I assume
that there should be a cell for the adc to select which dlft it is connected
to.
There have already been lengthy discussions in the past about a DFSDM peripheral on STM32MP1, which has features similar to those of the MDF and similar implementation constraints. For the DFSDM, a solution based on an IIO backend had been upstreamed. The MDF follows the same architecture. I need to take a little time to dive back into this issue.
DFSDM sources:
drivers/iio/adc/stm32-dfsdm-adc.c
drivers/iio/adc/stm32-dfsdm-core.c
Here is a sample of DFSDM DT
sd_adc0: simple-sd-adc0 {
compatible = "sd-modulator";
#io-backend-cells = <0>;
vref-supply = <&v3v3>;
};
dfsdm0 {
compatible = "st,stm32-dfsdm-adc";
...
channel@0 {
reg = <0>;
label = "in0";
...
io-backends = <&sd_adc0>;
};
};
I think all of these child nodes should just get deleted - all your
devices here seem completely fake, since you've got stuff that's only a
single word wide. With that, you could also throw away these mickey
mouse nodes with sound-dai-cels of 0, and use 1 instead, with that cell
again determining which dlft is in use.
The only child node I can really thing of any justification for here is
channels - albeit not adc channels since this is not an adc - so that
you can individually configure a dlft using those channel nodes.
These serial inputs, what is the source for the data that is ever
actually sent there? I am assuming it's effectively another IIO device,
just not the onboard adc? Are the outputs exposed on pins on the
package?
I would encourage you to remodel this system, where this device is the
backend and also try to get rid of as much of the consuming your own
clock as possible. Certainly consuming ker_clk should never be required.
It's hard to reason about what should happen with the serial interface
clocks, when I have no idea what the input/data source device actually
is in those cases. Being a clock controller does make sense, because the
device exposes CCK0/1 to the outside world, it's the internal routing to
the SITF blocks that I am not sure how to deal with. A ouroboros device
that is consuming a clock it provides is not really a done thing,
hopefully the IIO guys can tell you how these kinds of things are
typically done here, since I'm sure there's plenty of other devices
that have some sort of ability to change the clock source for a channel.
Probably you need to add two optional input clocks to this device, since
mdf_cck0/1 can be inputs too?
Let me know if any of this feedback is intractable stuff, and maybe hang
on for someone like David or Jonathan to provide some review before
going about a significant rework. It's worth bearing in mind that I am a
binding reviewer and not a domain expert in ADCs etc.
Thanks,
Conor.
Best regards
Olivier
+
+ properties:
+ compatible:
+ enum:
+ - st,stm32mp25-sitf-mdf
+
+ reg:
+ description: Specify the SITF serial interface instance
+ maxItems: 1
+
+ clocks:
+ description: |
+ Serial interface clock (optional depending on interface mode)
+ maxItems: 1
+
+ st,sitf-mode:
+ description: |
+ Select serial interface protocol
+ - spi: SPI mode
+ - lf_spi: low frequency SPI mode for low power applications
+ $ref: /schemas/types.yaml#/definitions/string
+ enum:
+ - spi
+ - lf_spi
+
+ required:
+ - reg
+ - st,sitf-mode
+
+ additionalProperties: false
+
+ "^filter@[0-9]+$":
+ type: object
+ description: Digital filter path child node
+
+ properties:
+ compatible:
+ enum:
+ - st,stm32mp25-mdf-dmic
+ - st,stm32mp25-mdf-adc
+
+ reg:
+ description: Specify the MDF filter instance
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ description: Internal clock used for MDF digital processing and control blocks.
+
+ clock-names:
+ items:
+ - const: ker_ck
+
+ dmas:
+ maxItems: 1
+
+ dma-names:
+ items:
+ - const: rx
+
+ "#io-channel-cells":
+ const: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ st,cic-mode:
+ description: |
+ Cascaded-integrator-comb (CIC) filter configuration
+ - 0: MCIC & ACIC filters in FastSinc mode
+ - [1-3]: MCIC & ACIC filters in Sinc mode order 1 to 3
+ - [4-5]: Single CIC filter in Sinc mode order 4 to 5
+ For audio purpose it is recommended to use CIC Sinc4 or Sinc5
+ This property is mandatory for filter 0 or filters not used in interleave mode.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 5
+
+ st,delay:
+ description: Filter delay in samples
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 127
+
+ st,rs-filter-bypass:
+ description: Bypass RSFLT reshaping filter.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,hpf-filter-cutoff-bp:
+ description: |
+ High Pass Filter (HPF) cut-off frequency expressed as a fraction of the PCM sampling rate.
+ Cut-off frequency = st,hpf-filter-cutoff-bp x Fpcm / 10000.
+ If this property is not defined the HPF is disabled.
+ enum: [625, 1250, 2500, 9500]
+
+ st,sync:
+ description:
+ Synchronize to another filter.
+ Must contain the phandle of the filter providing the synchronization.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/phandle-array
+ - maxItems: 1
+
+ st,sitf:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: Phandle of the serial interface connected to the digital filter
+ - description: |
+ The phandle's argument selects the bitstream on the falling or rising edge
+ of the serial interface clock:
+ - 0: rising edge
+ - 1: falling edge
+ enum: [0, 1]
+ default: 0
+ description:
+ Should be phandle/bitstream pair.
+
+ required:
+ - compatible
+ - reg
+ - interrupts
+ - dmas
+ - dma-names
+ - "#io-channel-cells"
+ - "#address-cells"
+ - "#size-cells"
+ - st,sitf
+
+ unevaluatedProperties: false
+
+ patternProperties:
+ "^channel@([0-7])$":
+ type: object
+ $ref: adc.yaml
+ description: Represents the external channel which is connected to the MDF.
+
+ properties:
+ reg:
+ maximum: 7
+
+ io-backends:
+ description:
+ Used to pipe external sigma delta modulator or internal ADC backend to MDF
+ channel.
+ maxItems: 1
+
+ required:
+ - reg
+
+ unevaluatedProperties: false
+
+ allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: st,stm32mp25-mdf-adc
+
+ then:
+ patternProperties:
+ "^channel@[0-7]$":
+ required:
+ - io-backends
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: st,stm32mp25-mdf-dmic
+
+ then:
+ patternProperties:
+ "^mdf-dai+$":
+ type: object
+ description: child node
+
+ properties:
+ compatible:
+ enum:
+ - st,stm32mp25-mdf-dai
+
+ "#sound-dai-cells":
+ const: 0
+
+ io-channels:
+ description:
+ From common IIO binding. Used to pipe external sigma delta
+ modulator or internal ADC output to MDF channel.
+
+ power-domains:
+ maxItems: 1
+
+ port:
+ $ref: /schemas/sound/audio-graph-port.yaml#
+ unevaluatedProperties: false
+
+ required:
+ - compatible
+ - "#sound-dai-cells"
+ - io-channels
+
+ additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/st,stm32mp25-rcc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ mdf1: mdf@504d0000 {
+ compatible = "st,stm32mp25-mdf";
+ ranges = <0 0x504d0000 0x1000>;
+ reg = <0x504d0000 0x8>, <0x504d0ff0 0x10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&rcc CK_KER_MDF1>;
+ clock-names = "ker_ck";
+ clock-ranges;
+ #clock-cells = <1>;
+ clock-output-names = "cck0", "cck1";
+ clock-frequency = <2048000>;
+
+ sitf5: sitf@300 {
+ compatible = "st,stm32mp25-sitf-mdf";
+ reg = <0x300 0x4>;
+ st,sitf-mode = "spi";
+ clocks = <&mdf1 0>;
+ };
+
+ filter0: filter@84 {
+ compatible = "st,stm32mp25-mdf-dmic";
+ reg = <0x84 0x70>;
+ #io-channel-cells = <1>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&hpdma 63 0x63 0x12 0>;
+ dma-names = "rx";
+ st,cic-mode = <5>;
+ st,sitf = <&sitf5 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ };
+
+ asoc_pdm0: mdf-dai {
+ compatible = "st,stm32mp25-mdf-dai";
+ #sound-dai-cells = <0>;
+ io-channels = <&filter0 0>;
+ };
+ };
+
+ filter1: filter@104 {
+ compatible = "st,stm32mp25-mdf-adc";
+ reg = <0x104 0x70>;
+ #io-channel-cells = <1>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&hpdma 64 0x63 0x12 0>;
+ dma-names = "rx";
+ st,cic-mode = <2>;
+ st,sitf = <&sitf5 1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@1 {
+ reg = <1>;
+ settling-time-us = <1000>;
+ io-backends = <&sd_adc1>;
+ };
+ };
+ };
+
+...
--
2.43.0