Re: [PATCH V3 04/19] accel/amdxdna: Upgrade firmware version to 6.0
From: Lizhi Hou
Date: Thu Oct 08 2026 - 13:15:56 EST
On 10/7/26 20:23, David Zhang wrote:
Upgrade firmware interface version to 6.0. Update host queue layout,
opcode definitions, and context creation/destruction request structures.
Parse priority band and PASID for hardware context creation. Protocol
compatibility for this queue layout is validated against the CERT
firmware protocol version.
Maybe the patch should be "Support firmware 6.0?" and mention fw 5.0 is obsoleted and will not be released.
Lizhi
Signed-off-by: David Zhang <yidong.zhang@xxxxxxx>
---
drivers/accel/amdxdna/aie4_ctx.c | 23 ++++++++++++++++++++---
drivers/accel/amdxdna/aie4_host_queue.h | 7 +++++--
drivers/accel/amdxdna/aie4_message.c | 11 +++++++++++
drivers/accel/amdxdna/aie4_msg_priv.h | 20 +++++++++++++++++---
drivers/accel/amdxdna/aie4_pci.h | 1 +
drivers/accel/amdxdna/npu3_regs.c | 2 +-
6 files changed, 55 insertions(+), 9 deletions(-)
diff --git a/drivers/accel/amdxdna/aie4_ctx.c b/drivers/accel/amdxdna/aie4_ctx.c
index 8157f2a6fd10..5eb918e1d58c 100644
--- a/drivers/accel/amdxdna/aie4_ctx.c
+++ b/drivers/accel/amdxdna/aie4_ctx.c
@@ -9,6 +9,7 @@
#include <drm/drm_gem_shmem_helper.h>
#include <drm/drm_print.h>
#include <drm/gpu_scheduler.h>
+#include <linux/iommu.h>
#include <linux/types.h>
#include "aie.h"
@@ -110,6 +111,22 @@ static int aie4_msg_destroy_context(struct amdxdna_dev_hdl *ndev, u32 hw_context
return aie_send_mgmt_msg_wait(&ndev->aie, &msg);
}
+static u8 aie4_parse_priority_to_dev(u32 priority)
+{
+ switch (priority) {
+ case AMDXDNA_QOS_LOW_PRIORITY:
+ return AIE4_CONTEXT_PRIORITY_BAND_IDLE;
+ case AMDXDNA_QOS_NORMAL_PRIORITY:
+ return AIE4_CONTEXT_PRIORITY_BAND_NORMAL;
+ case AMDXDNA_QOS_HIGH_PRIORITY:
+ return AIE4_CONTEXT_PRIORITY_BAND_FOCUS;
+ case AMDXDNA_QOS_REALTIME_PRIORITY:
+ return AIE4_CONTEXT_PRIORITY_BAND_REAL_TIME;
+ default:
+ return AIE4_CONTEXT_PRIORITY_BAND_NORMAL;
+ }
+}
+
static int aie4_hwctx_create(struct amdxdna_hwctx *hwctx)
{
DECLARE_AIE_MSG(aie4_msg_create_hw_context, AIE4_MSG_OP_CREATE_HW_CONTEXT);
@@ -129,9 +146,9 @@ static int aie4_hwctx_create(struct amdxdna_hwctx *hwctx)
req.partition_id = ndev->partition_id;
req.request_num_tiles = hwctx->num_tiles;
- req.pasid = FIELD_PREP(AIE4_MSG_PASID, client->pasid) |
- FIELD_PREP(AIE4_MSG_PASID_VLD, 1);
- req.priority_band = hwctx->qos.priority;
+ req.pasid = aie4_msg_pasid(client);
+ req.pasid = req.pasid == IOMMU_PASID_INVALID ? 0 : req.pasid;
+ req.priority_band = aie4_parse_priority_to_dev(hwctx->qos.priority);
req.hsa_addr_high = upper_32_bits(amdxdna_gem_dev_addr(priv->umq_bo));
req.hsa_addr_low = lower_32_bits(amdxdna_gem_dev_addr(priv->umq_bo));
diff --git a/drivers/accel/amdxdna/aie4_host_queue.h b/drivers/accel/amdxdna/aie4_host_queue.h
index 1b33eda3f727..95ebbb714c6f 100644
--- a/drivers/accel/amdxdna/aie4_host_queue.h
+++ b/drivers/accel/amdxdna/aie4_host_queue.h
@@ -10,6 +10,7 @@
#define CTX_MAX_CMDS 32
+/* Host queue header layout. */
struct host_queue_header {
__u64 read_index;
struct {
@@ -17,8 +18,10 @@ struct host_queue_header {
__u16 minor;
} version;
__u32 capacity; /* Queue capacity, must be power of two. */
- __u64 write_index;
+ __u64 padding0[6];
+ __u64 write_index; /* different cacheline from read_index to avoid false sharing */
+ __u64 padding1[6];
__u64 data_address; /* The xdna dev addr for payload. */
-};
+} __packed;
#endif /* _AIE4_HOST_QUEUE_H_ */
diff --git a/drivers/accel/amdxdna/aie4_message.c b/drivers/accel/amdxdna/aie4_message.c
index b137a2a40b34..bdbd1d116b61 100644
--- a/drivers/accel/amdxdna/aie4_message.c
+++ b/drivers/accel/amdxdna/aie4_message.c
@@ -5,6 +5,8 @@
#include <drm/amdxdna_accel.h>
#include <drm/drm_print.h>
+#include <linux/bitfield.h>
+#include <linux/iommu.h>
#include <linux/mutex.h>
#include "aie.h"
@@ -14,6 +16,15 @@
#include "amdxdna_mailbox_helper.h"
#include "amdxdna_pci_drv.h"
+u32 aie4_msg_pasid(struct amdxdna_client *client)
+{
+ if (!amdxdna_pasid_on(client))
+ return IOMMU_PASID_INVALID;
+
+ return FIELD_PREP(AIE4_MSG_PASID, client->pasid) |
+ FIELD_PREP(AIE4_MSG_PASID_VLD, 1);
+}
+
int aie4_suspend_fw(struct amdxdna_dev_hdl *ndev)
{
DECLARE_AIE_MSG(aie4_msg_suspend, AIE4_MSG_OP_SUSPEND);
diff --git a/drivers/accel/amdxdna/aie4_msg_priv.h b/drivers/accel/amdxdna/aie4_msg_priv.h
index 5b97c8057de0..b9f7c61f36e3 100644
--- a/drivers/accel/amdxdna/aie4_msg_priv.h
+++ b/drivers/accel/amdxdna/aie4_msg_priv.h
@@ -12,7 +12,6 @@
enum aie4_msg_opcode {
AIE4_MSG_OP_IDENTIFY = 0x10002,
AIE4_MSG_OP_SUSPEND = 0x10003,
- AIE4_MSG_OP_ATTACH_WORK_BUFFER = 0x1000D,
AIE4_MSG_OP_QUERY_CERT_FIRMWARE_VERSION = 0x1000F,
AIE4_MSG_OP_CREATE_VFS = 0x20001,
@@ -23,6 +22,8 @@ enum aie4_msg_opcode {
AIE4_MSG_OP_CREATE_HW_CONTEXT = 0x30003,
AIE4_MSG_OP_DESTROY_HW_CONTEXT = 0x30004,
AIE4_MSG_OP_AIE_TILE_INFO = 0x30006,
+
+ AIE4_MSG_OP_ATTACH_WORK_BUFFER = 0x40001,
};
enum aie4_msg_status {
@@ -32,6 +33,14 @@ enum aie4_msg_status {
MAX_AIE4_MSG_STATUS_CODE = 0x4,
};
+enum aie4_msg_context_priority_band {
+ AIE4_CONTEXT_PRIORITY_BAND_IDLE = 0,
+ AIE4_CONTEXT_PRIORITY_BAND_NORMAL,
+ AIE4_CONTEXT_PRIORITY_BAND_FOCUS,
+ AIE4_CONTEXT_PRIORITY_BAND_REAL_TIME,
+ AIE4_CONTEXT_PRIORITY_BAND_COUNT
+};
+
struct aie4_msg_identify_req {
__u32 rsvd;
} __packed;
@@ -94,7 +103,9 @@ struct aie4_msg_create_hw_context_req {
#define AIE4_MSG_PASID GENMASK(19, 0)
#define AIE4_MSG_PASID_VLD GENMASK(31, 31)
__u32 pasid;
- __u32 priority_band;
+ __u8 priority_band;
+ __u8 priority_level;
+ __u16 restore_id;
} __packed;
struct aie4_msg_create_hw_context_resp {
@@ -106,11 +117,14 @@ struct aie4_msg_create_hw_context_resp {
struct aie4_msg_destroy_hw_context_req {
__u32 hw_context_id;
- __u32 resvd1;
+#define AIE4_MSG_GRACEFUL_FLAG GENMASK(0, 0)
+ __u32 graceful_flag;
} __packed;
struct aie4_msg_destroy_hw_context_resp {
enum aie4_msg_status status;
+ __u16 restore_id;
+ __u16 resvd;
} __packed;
struct aie4_tile_info {
diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h
index 8c62ee6a9b23..bdbb2d7cf0e7 100644
--- a/drivers/accel/amdxdna/aie4_pci.h
+++ b/drivers/accel/amdxdna/aie4_pci.h
@@ -75,6 +75,7 @@ int aie4_query_npu_firmware_version(struct amdxdna_dev_hdl *ndev,
struct amdxdna_drm_query_firmware_version *fw_version);
int aie4_query_cert_firmware_version(struct amdxdna_dev_hdl *ndev,
struct amdxdna_drm_query_firmware_version *cert_version);
+u32 aie4_msg_pasid(struct amdxdna_client *client);
/* aie4_ctx.c */
int aie4_hwctx_init(struct amdxdna_hwctx *hwctx);
diff --git a/drivers/accel/amdxdna/npu3_regs.c b/drivers/accel/amdxdna/npu3_regs.c
index e82bc0a4f597..93f749acb5d5 100644
--- a/drivers/accel/amdxdna/npu3_regs.c
+++ b/drivers/accel/amdxdna/npu3_regs.c
@@ -38,7 +38,7 @@
#define MP1_C2PMSG_60_ALT_1 0x3B109F0
static const struct amdxdna_fw_feature_tbl npu3_fw_feature_table[] = {
- { .major = 5, .min_minor = 10 },
+ { .major = 6, .min_minor = 0 },
{ 0 }
};