[PATCH 3/5] arm64: dts: qcom: nord: Add Adreno 753 GPU and GMU nodes

[Akhil P Oommen]

From: Shivam Rawat <shivrawa@xxxxxxxxxxxxxxxx>

Nord SoC integrates an Adreno 753 GPU as its primary GPU, belonging to
the A7xx Gen3 family, along with its Graphics Management Unit (GMU).

Add the GPU and GMU nodes together with their OPP tables. The GPU sits
behind adreno_smmu_0 and uses the gen71300 zap shader, while the GMU is
clocked and powered from GPUCC.

Unlike previous Adreno SoCs, where the GMU AXI clock comes from the
single global clock controller, Nord splits its GCC into four blocks
(GCC, SE_GCC, NE_GCC and NW_GCC). The GPU's AXI clock,
NW_GCC_HSCNOC_GPU_AXI_CLK, is provided by NW_GCC, so the GMU node
references nwgcc directly.

Signed-off-by: Shivam Rawat <shivrawa@xxxxxxxxxxxxxxxx>
Signed-off-by: Akhil P Oommen <akhilpo@xxxxxxxxxxxxxxxx>
---
 arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 116 ++++++++++++++++++++++++++++
 1 file changed, 116 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
index 1ab7d9bc3cfe..4379092b7bf8 100644
--- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
+++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
@@ -776,6 +776,122 @@ hscnoc: interconnect@2000000 {
 		qcom,bcm-voters = <&apps_bcm_voter>;
 	};
 
+	gpu_0: gpu@3d00000 {
+		compatible = "qcom,adreno-43051701", "qcom,adreno";
+		reg = <0x0 0x03d00000 0x0 0x40000>,
+		      <0x0 0x03d9e000 0x0 0x2000>,
+		      <0x0 0x03d61000 0x0 0x800>;
+		reg-names = "kgsl_3d0_reg_memory",
+			    "cx_mem",
+			    "cx_dbgc";
+
+		interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+		iommus = <&adreno_smmu_0 0 0x0>,
+			 <&adreno_smmu_0 1 0x0>;
+
+		operating-points-v2 = <&gpu_opp_table_0>;
+
+		qcom,gmu = <&gmu_0>;
+		#cooling-cells = <2>;
+
+		interconnects = <&hscnoc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
+				 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+		interconnect-names = "gfx-mem";
+
+		status = "disabled";
+
+		gpu_0_zap_shader: zap-shader {
+			memory-region = <&gpu_microcode_mem>;
+		};
+
+		gpu_opp_table_0: opp-table {
+			compatible = "operating-points-v2-adreno",
+				     "operating-points-v2";
+
+			opp-468000000 {
+				opp-hz = /bits/ 64 <468000000>;
+				opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+				opp-peak-kBps = <781250>;
+			};
+
+			opp-625000000 {
+				opp-hz = /bits/ 64 <625000000>;
+				opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+				opp-peak-kBps = <6075000>;
+			};
+
+			opp-735000000 {
+				opp-hz = /bits/ 64 <735000000>;
+				opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+				opp-peak-kBps = <8175000>;
+			};
+
+			opp-854000000 {
+				opp-hz = /bits/ 64 <854000000>;
+				opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+				opp-peak-kBps = <10687500>;
+			};
+
+			opp-1000000000 {
+				opp-hz = /bits/ 64 <1000000000>;
+				opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+				opp-peak-kBps = <12450000>;
+			};
+		};
+	};
+
+	gmu_0: gmu@3d6a000 {
+		compatible = "qcom,adreno-gmu-753.1", "qcom,adreno-gmu";
+		reg = <0x0 0x03d6a000 0x0 0x35000>,
+		      <0x0 0x03d50000 0x0 0x10000>,
+		      <0x0 0x0b2a0000 0x0 0x10000>;
+		reg-names = "gmu",
+			    "rscc",
+			    "gmu_pdc";
+
+		interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "hfi",
+				  "gmu";
+
+		clocks = <&gpucc GPU_CC_AHB_CLK>,
+			 <&gpucc GPU_CC_CX_GMU_CLK>,
+			 <&gpucc GPU_CC_CXO_CLK>,
+			 <&nwgcc NW_GCC_HSCNOC_GPU_AXI_CLK>,
+			 <&gpucc GPU_CC_MEMNOC_GFX_CLK>,
+			 <&gpucc GPU_CC_HUB_CX_INT_CLK>;
+		clock-names = "ahb",
+			      "gmu",
+			      "cxo",
+			      "axi",
+			      "memnoc",
+			      "hub";
+
+		power-domains = <&gpucc GPU_CC_CX_GDSC>,
+				<&gpucc GPU_CC_GX_GDSC>;
+		power-domain-names = "cx",
+				     "gx";
+
+		iommus = <&adreno_smmu_0 5 0x0>;
+
+		operating-points-v2 = <&gmu_opp_table_0>;
+
+		gmu_opp_table_0: opp-table {
+			compatible = "operating-points-v2";
+
+			opp-416666000 {
+				opp-hz = /bits/ 64 <416666000>;
+				opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+			};
+
+			opp-625000000 {
+				opp-hz = /bits/ 64 <625000000>;
+				opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+			};
+		};
+	};
+
 	gpucc: clock-controller@3d90000 {
 		compatible = "qcom,nord-gpucc";
 		reg = <0x0 0x03d90000 0x0 0x9800>;

-- 
2.55.0