[PATCH v3 0/2] perf riscv: Implement rdtsc()

[Chen Pei]

tools/perf falls back to the __weak rdtsc() stub in tools/perf/util/tsc.c
on every architecture that does not override it, riscv included.  The
stub returns a constant 0, so anything that reaches for the counter gets
a value that means nothing and cannot tell it apart from a counter that
happens to be at 0.

The time CSR is a natural TSC equivalent on riscv: readable from user
mode, constant frequency, and the same counter that riscv's
arch_perf_update_userpage() feeds the user page conversion fields from,
ever since commit 83c5e13b8cbb ("riscv: Prepare for user-space perf
event mmap support").  This series registers that on the tools side.

The two patches are split so that the first stands on its own:

1. Implement rdtsc() over the time CSR for riscv64.

2. Have the build system say which architectures have a usable counter,
   instead of a list of compiler macros inside the test.

What this is worth beyond the subtest result:

1. The subtest is the only reader of those conversion fields riscv
   can run, so it guards arithmetic that has shipped unexercised;
   registering the counter at the same time leaves a future riscv
   auxtrace driver the reading and the conversion already in place.

2. The flag lets a caller ask whether the architecture has a counter
   before it uses the value, without keeping its own copy of a list
   that has to be edited every time an architecture grows an
   implementation.

Changes since v2:
- Key off IS_BUILTIN(HAVE_RDTSC), with <tools/config.h> included, instead
  of an #ifndef block, as Adrian Hunter suggested.
- Collected the tags received on v2.

Changes since v1:
- Define rdtsc() for RV64 only. RV32 now keeps the weak stub.
- Declare the capability through the build system rather than through a
  weak arch__rdtsc_supported() hook, following the PERF_HAVE_JITDUMP
  pattern, as Leo Yan suggested.

Tests:
======
- Build side, this version: the compile command of
  tests/perf-time-to-tsc.o carries -DHAVE_RDTSC on riscv64, arm64 and the
  x86_64 host, and does not on riscv32, so RV32 stays on the weak stub.
- Same object built on the host with and without the flag: with it the
  "TSC support" subtest returns TEST_OK with the skip branch folded out,
  without it the pr_debug and the TEST_SKIP branch are still there.  That
  is the branch the #ifndef used to pick, so the change is behaviour
  preserving.
- riscv64 QEMU virt guest with sscofpmf, as reported on v2: before the
  series the "TSC support" subtest skips and the conversion subtest fails
  while comparing against the stub's constant 0; after, both report Ok.
  Patch 1 is unchanged here and the subtest decision is behaviour
  preserving, so v3 was verified on the build side only.

Chen Pei (2):
  perf riscv: Implement rdtsc()
  perf tsc: Declare TSC support from the build system

 tools/perf/Makefile.config          |  4 ++++
 tools/perf/arch/arm64/Makefile      |  1 +
 tools/perf/arch/riscv/Makefile      |  1 +
 tools/perf/arch/riscv/util/Build    |  1 +
 tools/perf/arch/riscv/util/tsc.c    | 27 +++++++++++++++++++++++++++
 tools/perf/arch/x86/Makefile        |  1 +
 tools/perf/tests/perf-time-to-tsc.c | 14 ++------------
 7 files changed, 37 insertions(+), 12 deletions(-)
 create mode 100644 tools/perf/arch/riscv/util/tsc.c

-- 
2.50.1