[PATCH v2 6/6] arm64: dts: cix: Describe the Sky1 DMA-350 bus integration
From: Jelly Jia
Date: Fri Oct 09 2026 - 01:19:41 EST
The FCH DMA-350 controller sits behind an interconnect window, so the
addresses its DMA master uses differ from the CPU physical addresses.
Describe the integration as a bus node carrying the dma-ranges of that
window, with the controller itself as a child, and give the controller
the SoC compatible and the clock feeding it.
The AUDSS DMA-350 controller is described the same way, with its clock,
reset and the AUDSS CRU syscon that gates the channel interrupts before
they reach the AP interrupt controller. It has no consumer in the SoC
dtsi yet: the audio controllers that use it are not described upstream.
Assisted-by: LLM checkpatch sparse dt_binding_check dtbs_check
Signed-off-by: Jelly Jia <Jelly.Jia@xxxxxxxxxxx>
---
v1 -> v2:
- The DMA-350 nodes are no longer wrappers with the generic controller
as a child: each Sky1 DMA-350 is a single device node with the
"cix,sky1-dma350", "arm,dma-350" compatible, its real MMIO region and
the integration resources (clock, reset, interrupt router) that v1 kept
on the wrapper. The integration and the block are one device, and the
MMIO is the same as the generic node it replaces.
- The FCH and AUDSS DMA-350 masters sit behind SoC interconnect windows
in a static DMA address domain: the AUDSS masters see the audio
register and FIFO block at 0x20000000 and the DRAM window at
0x30000000, which the CPU sees at 0x07010000 and 0xc0000000, and the
FCH masters see the 0x040b0000 window at 0x040a0000. Their DMA view of
the address space is not the CPU physical view.
- The windows are static hardware configuration, set up before Linux
starts by the boot firmware / secure world: they are not programmable
from Linux and must not be reconfigured by it. There is nothing for a
Linux interconnect provider to manage here, so the translation cannot
be modeled as one; it is a fixed property of the bus.
- It is described the standard devicetree way instead: a generic
"simple-bus" parent with an identity "ranges;" and the "dma-ranges" of
the window. This is not the rejected v1 wrapper and not a separate DMA
wrapper/integration device: the parent has no device-specific or
vendor wrapper compatible, only the generic "simple-bus" compatible,
no reg, no clocks, no resets, no driver and no private address
translation. Its only job is to carry the static translation, so it is
only a generic bus/address-domain node.
- The "dma-ranges" have to sit on that parent for the OF core to build
dev->dma_range_map: of_dma_configure_id() starts the lookup at the
device's parent (bus_np = __of_get_dma_parent(np) in
drivers/of/device.c), so a "dma-ranges" on the controller node itself
would be ignored. The translation is applied by the DMA API, not by
driver code: the driver maps slave resources with dma_map_resource()
and contains no address parser.
- The same shape is used in mainline: the Agilex5 DMA bus
(dma-bus@10db0000, a simple-bus with dma-ranges whose controller
carries "altr,agilex5-axi-dma", "snps,axi-dma-1.01a") and the Marvell
AC5 buses (bus@80500000 with "ranges;" and "dma-ranges", and
behind-32bit-controller@7f000000, whose only purpose is the DMA
mapping of the devices below it).
arch/arm64/boot/dts/cix/sky1.dtsi | 66 +++++++++++++++++++++++++------
1 file changed, 54 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi
index 0a820f45feb9..e3bd6c0e383f 100644
--- a/arch/arm64/boot/dts/cix/sky1.dtsi
+++ b/arch/arm64/boot/dts/cix/sky1.dtsi
@@ -518,18 +518,29 @@ iomuxc: pinctrl@4170000 {
reg = <0x0 0x04170000 0x0 0x1000>;
};
- fch_dmac: dma-controller@4190000 {
- compatible = "arm,dma-350";
- reg = <0x0 0x4190000 0x0 0x10000>;
- interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>;
- #dma-cells = <1>;
+ bus@4190000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-ranges = <0x0 0x040a0000 0x0 0x040b0000 0x0 0x00040000>,
+ <0x0 0x80000000 0x0 0x80000000 0x8 0x00000000>,
+ <0x80 0x00000000 0x80 0x00000000 0x80 0x00000000>;
+
+ fch_dmac: dma-controller@4190000 {
+ compatible = "cix,sky1-dma350", "arm,dma-350";
+ reg = <0x0 0x04190000 0x0 0x10000>;
+ clocks = <&scmi_clk CLK_TREE_FCH_DMA_ACLK>;
+ interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>;
+ #dma-cells = <1>;
+ };
};
mbox_ap2se: mailbox@5060000 {
@@ -576,6 +587,37 @@ mbox_pm2ap: mailbox@65a0080 {
cix,mbox-dir = "rx";
};
+ bus@7010000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-ranges = <0x0 0x20000000 0x0 0x07010000 0x0 0x00100000>,
+ <0x0 0x30000000 0x0 0xc0000000 0x0 0x20000000>;
+
+ audss_dmac: dma-controller@7010000 {
+ compatible = "cix,sky1-dma350", "arm,dma-350";
+ reg = <0x0 0x07010000 0x0 0x10000>;
+ clocks = <&audss_cru CLK_DMAC_AXI>;
+ resets = <&audss_cru AUDSS_DMAC_SW_RST>;
+ /*
+ * The AUDSS CRU gates each DMAC channel interrupt
+ * before it reaches the GIC. AUDSS_DMAC_INFO_AP_IRQ
+ * is at CRU offset 0x54.
+ */
+ cix,irq-router = <&audss_cru>;
+ interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH 0>;
+ #dma-cells = <1>;
+ };
+ };
+
audss_cru: clock-controller@7110000 {
compatible = "cix,sky1-audss-cru";
reg = <0x0 0x07110000 0x0 0x10000>;
--
2.54.0