Re: [PATCH v4] arm64: errata: Add NXP iMX8QM workaround for A53 cache coherency issue

[Catalin Marinas]

On Thu, Oct 08, 2026 at 09:23:31PM +0800, Peng Fan wrote:
> On Tue, Oct 06, 2026 at 12:18:42PM +0100, Catalin Marinas wrote:
> >On Mon, Aug 24, 2026 at 12:02:04PM +0800, Peng Fan (OSS) wrote:
> >>   - Disabling KVM since correct TLB maintenance cannot be guaranteed
> >>     for guests.
> >
> >Do you need virtualisation on such platform? An alternative would be for
> 
> We not have KVM support in our software release for i.MX8QM.
> 
> >the guests to be aware of the erratum as well and use the right TLBI/IC
> >ops. But you'd also need to upgrade the VMID-aware ops in KVM (unless
> >the hardware can't work around stage 2 TLBI at all).
> 
> We not have test cases for this since KVM is not in our release scope. 
> Could we take this as a future enablement to avoid uneccessary churn

Yes, you can leave it out if you don't care about the KVM use-cases.

> >There's a precedent with 4311569 to wire up a SoC erratum into the CPU
> >errata framework. That one is a system wide feature, so only probed once
> >for the CPUs coming up at boot (though still probed for each late CPUs).
> >For iMX, you need this turned on early, hence the boot probing. But
> >calling it a strict boot CPU feature is a bit of a stretch. It also gets
> >probed on every CPU, unnecessarily.
> >
> >I think we could do with something like below (maybe as a preparatory
> >patch). We could also add it to 4311569 even if it changes its scope
> >from system to boot CPU (the early param is available).
> >
> >Only compile-tested and haven't tried wiring up your workaround:
> 
> With type set to ARM64_CPUCAP_SOC_ERRATUM for i.MX8QM and your patch
> applied, I not see issues in my test.
> 
> Would you post it as a formal patch or need me to include your patch
> with i.MX8QM errata patch in a patchset?

Please post it with your patchset. Feel free to add a co-developed-by or
suggested-by me on the new cpucap proposal.

-- 
Catalin