[PATCH v2 10/14] clk: samsung: exynos8855: add block usb clock support
From: Raghav Sharma
Date: Fri Oct 09 2026 - 07:55:10 EST
Register compatible and cmu_info data to support clocks.
CMU_USB, this provides clocks for USB
Co-developed-by: Alim Akhtar <alim.akhtar@xxxxxxxxxxx>
Signed-off-by: Alim Akhtar <alim.akhtar@xxxxxxxxxxx>
Signed-off-by: Raghav Sharma <raghav.s@xxxxxxxxxxx>
---
drivers/clk/samsung/clk-exynos8855.c | 78 ++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos8855.c b/drivers/clk/samsung/clk-exynos8855.c
index 16d71db11ad0..010ca79116d3 100644
--- a/drivers/clk/samsung/clk-exynos8855.c
+++ b/drivers/clk/samsung/clk-exynos8855.c
@@ -20,11 +20,13 @@
#define CLKS_NR_PERIC (CLK_GOUT_USI_PERIC + 1)
#define CLKS_NR_PERIS (CLK_GOUT_WDT1_PERIS + 1)
#define CLKS_NR_HSI (CLK_GOUT_SYSREG_HSI + 1)
+#define CLKS_NR_USB (CLK_GOUT_SYSREG_USB + 1)
#define EXYNOS8855_HSI_GATE_DBG_OFFSET 0x2000
#define EXYNOS8855_PERIS_GATE_DBG_OFFSET 0x2004
#define EXYNOS8855_PERIC_GATE_DBG_OFFSET 0x2024
#define EXYNOS8855_TOP_GATE_DBG_OFFSET 0x20A0
+#define EXYNOS8855_USB_GATE_DBG_OFFSET 0x2004
#define EXYNOS8855_DRCG_EN_OFFSET 0x104
#define EXYNOS8855_MEMCLK_OFFSET 0x108
@@ -1261,6 +1263,79 @@ static const struct samsung_cmu_info hsi_cmu_info __initconst = {
.memclk_offset = EXYNOS8855_MEMCLK_OFFSET,
};
+/* ---- CMU_USB --------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_USB (0x13000000) */
+#define CMU_USB_PLL_CON0_MUX_CLKCMU_USB_NOC_USER 0x600
+#define CMU_USB_PLL_CON0_MUX_CLKCMU_USB_USB20DRD_USER 0x610
+#define CMU_USB_CLK_CON_MUX_CLK_USB_USB20DRD 0x1000
+#define CMU_USB_CLK_CON_DIV_CLK_USB_NOC_DIV3 0x1800
+#define CMU_USB_CLK_CON_GAT_BLK_USB_UID_CMU_USB_IPCLKPORT_PCLK 0x2000
+#define CMU_USB_CLK_CON_GAT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK 0x2030
+#define CMU_USB_CONTROLLER_OPTION0_CMU_CTRL 0x800
+
+static const unsigned long usb_clk_regs[] __initconst = {
+ CMU_USB_PLL_CON0_MUX_CLKCMU_USB_NOC_USER,
+ CMU_USB_PLL_CON0_MUX_CLKCMU_USB_USB20DRD_USER,
+ CMU_USB_CLK_CON_MUX_CLK_USB_USB20DRD,
+ CMU_USB_CLK_CON_DIV_CLK_USB_NOC_DIV3,
+ CMU_USB_CLK_CON_GAT_BLK_USB_UID_CMU_USB_IPCLKPORT_PCLK,
+ CMU_USB_CLK_CON_GAT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK,
+ CMU_USB_CONTROLLER_OPTION0_CMU_CTRL,
+};
+
+/* List of parent clocks for Muxes in CMU_USB */
+PNAME(mout_clkcmu_usb_noc_user_p) = { "oscclk", "dout_clkcmu_usb_noc" };
+PNAME(mout_clkcmu_usb_usb20drd_user_p) = { "oscclk", "dout_clkcmu_usb_usb20drd" };
+PNAME(mout_clk_usb_usb20drd_p) = { "oscclk_usb_link", "mout_clkcmu_usb_usb20drd_user" };
+
+static const struct samsung_mux_clock usb_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_USB_NOC_USER, "mout_clkcmu_usb_noc_user",
+ mout_clkcmu_usb_noc_user_p, CMU_USB_PLL_CON0_MUX_CLKCMU_USB_NOC_USER, 4, 1),
+ MUX(CLK_MOUT_USB_USB20DRD_USER, "mout_clkcmu_usb_usb20drd_user",
+ mout_clkcmu_usb_usb20drd_user_p, CMU_USB_PLL_CON0_MUX_CLKCMU_USB_USB20DRD_USER, 4, 1),
+ MUX(CLK_MOUT_USB_USB20DRD, "mout_clk_usb_usb20drd",
+ mout_clk_usb_usb20drd_p, CMU_USB_CLK_CON_MUX_CLK_USB_USB20DRD, 0, 1),
+};
+
+static const struct samsung_div_clock usb_div_clks[] __initconst = {
+ DIV(CLK_DOUT_USB_NOC_DIV3, "dout_clkcmu_usb_noc_div3",
+ "mout_clkcmu_usb_noc_user", CMU_USB_CLK_CON_DIV_CLK_USB_NOC_DIV3,
+ 0, 4),
+};
+
+static const struct samsung_gate_clock usb_gate_clks[] __initconst = {
+ /* System will hang if this critical clock is gated */
+ GATE(CLK_GOUT_CMU_USB, "gout_cmu_usb",
+ "mout_clkcmu_usb_noc_user",
+ CMU_USB_CLK_CON_GAT_BLK_USB_UID_CMU_USB_IPCLKPORT_PCLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_SYSREG_USB, "gout_sysreg_usb",
+ "mout_clkcmu_usb_noc_user",
+ CMU_USB_CLK_CON_GAT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK,
+ 21, 0, 0),
+};
+
+static const struct samsung_cmu_info usb_cmu_info __initconst = {
+ .mux_clks = usb_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(usb_mux_clks),
+ .div_clks = usb_div_clks,
+ .nr_div_clks = ARRAY_SIZE(usb_div_clks),
+ .gate_clks = usb_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(usb_gate_clks),
+ .nr_clk_ids = CLKS_NR_USB,
+ .clk_regs = usb_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(usb_clk_regs),
+ .sysreg_clk_regs = dcrg_memclk_sysreg,
+ .nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_memclk_sysreg),
+ .clk_name = "bus",
+ .auto_clock_gate = true,
+ .gate_dbg_offset = EXYNOS8855_USB_GATE_DBG_OFFSET,
+ .option_offset = CMU_USB_CONTROLLER_OPTION0_CMU_CTRL,
+ .drcg_offset = EXYNOS8855_DRCG_EN_OFFSET,
+ .memclk_offset = EXYNOS8855_MEMCLK_OFFSET,
+};
+
static int __init exynos8855_cmu_probe(struct platform_device *pdev)
{
const struct samsung_cmu_info *info;
@@ -1285,6 +1360,9 @@ static const struct of_device_id exynos8855_cmu_of_match[] = {
}, {
.compatible = "samsung,exynos8855-cmu-top",
.data = &top_cmu_info,
+ }, {
+ .compatible = "samsung,exynos8855-cmu-usb",
+ .data = &usb_cmu_info,
},
{ }
};
--
2.34.1