[PATCH v2 08/14] clk: samsung: exynos8855: add block peris clock support
From: Raghav Sharma
Date: Fri Oct 09 2026 - 08:32:06 EST
Register compatible and cmu_info data to support clocks.
CMU_PERIS, this provides clocks for PERIS
Co-developed-by: Alim Akhtar <alim.akhtar@xxxxxxxxxxx>
Signed-off-by: Alim Akhtar <alim.akhtar@xxxxxxxxxxx>
Signed-off-by: Raghav Sharma <raghav.s@xxxxxxxxxxx>
---
drivers/clk/samsung/clk-exynos8855.c | 98 ++++++++++++++++++++++++++++
1 file changed, 98 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos8855.c b/drivers/clk/samsung/clk-exynos8855.c
index 5394706d214c..2bf889a478bc 100644
--- a/drivers/clk/samsung/clk-exynos8855.c
+++ b/drivers/clk/samsung/clk-exynos8855.c
@@ -18,7 +18,9 @@
/* NOTE: Must be equal to the last clock ID increased by one */
#define CLKS_NR_TOP (CLKCMU_DOUT_G3D_HTU + 1)
#define CLKS_NR_PERIC (CLK_GOUT_USI_PERIC + 1)
+#define CLKS_NR_PERIS (CLK_GOUT_WDT1_PERIS + 1)
+#define EXYNOS8855_PERIS_GATE_DBG_OFFSET 0x2004
#define EXYNOS8855_PERIC_GATE_DBG_OFFSET 0x2024
#define EXYNOS8855_TOP_GATE_DBG_OFFSET 0x20A0
@@ -1094,6 +1096,99 @@ static const struct samsung_cmu_info peric_cmu_info __initconst = {
.memclk_offset = EXYNOS8855_MEMCLK_OFFSET,
};
+/* ---- CMU_PERIS --------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_PERIS (0x10030000) */
+#define CMU_PERIS_PLL_CON0_MUX_CLKCMU_PERIS_NOC_USER 0x600
+#define CMU_PERIS_CLK_CON_MUX_CLK_PERIS_GIC 0x1000
+#define CMU_PERIS_PLL_CON0_MUX_CLK_PERIS_GIC_USER 0x610
+#define CMU_PERIS_CLK_CON_DIV_CLK_PERIS_NOCP 0x1800
+#define CMU_PERIS_CLK_CON_DIV_CLK_PERIS_OTP 0x1804
+#define CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_CMU_PERIS_IPCLKPORT_PCLK 0x201c
+#define CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK 0x2040
+#define CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK 0x2048
+#define CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK 0x204c
+#define CMU_PERIS_CONTROLLER_OPTION0_CMU_CTRL 0x800
+
+static const unsigned long peris_clk_regs[] __initconst = {
+ CMU_PERIS_PLL_CON0_MUX_CLKCMU_PERIS_NOC_USER,
+ CMU_PERIS_CLK_CON_MUX_CLK_PERIS_GIC,
+ CMU_PERIS_PLL_CON0_MUX_CLK_PERIS_GIC_USER,
+ CMU_PERIS_CLK_CON_DIV_CLK_PERIS_NOCP,
+ CMU_PERIS_CLK_CON_DIV_CLK_PERIS_OTP,
+ CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_CMU_PERIS_IPCLKPORT_PCLK,
+ CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
+ CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK,
+ CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK,
+ CMU_PERIS_CONTROLLER_OPTION0_CMU_CTRL,
+};
+
+/* List of parent clocks for Muxes in CMU_PERIS */
+PNAME(mout_clkcmu_peris_noc_user_p) = { "oscclk", "dout_clkcmu_peris_noc" };
+PNAME(mout_clk_peris_gic_p) = { "oscclk", "mout_clkcmu_peris_gic_user" };
+PNAME(mout_clkcmu_peris_gic_user_p) = { "oscclk", "dout_clkcmu_peris_gic" };
+
+static const struct samsung_mux_clock peris_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_PERIS_NOC_USER, "mout_clkcmu_peris_noc_user",
+ mout_clkcmu_peris_noc_user_p, CMU_PERIS_PLL_CON0_MUX_CLKCMU_PERIS_NOC_USER, 4, 1),
+ MUX(CLK_MOUT_PERIS_GIC, "mout_clk_peris_gic",
+ mout_clk_peris_gic_p, CMU_PERIS_CLK_CON_MUX_CLK_PERIS_GIC, 0, 1),
+ MUX(CLK_MOUT_PERIS_GIC_USER, "mout_clkcmu_peris_gic_user",
+ mout_clkcmu_peris_gic_user_p, CMU_PERIS_PLL_CON0_MUX_CLK_PERIS_GIC_USER, 4, 1),
+};
+
+static const struct samsung_div_clock peris_div_clks[] __initconst = {
+ DIV(CLK_DOUT_PERIS_NOCP, "dout_clkcmu_peris_nocp",
+ "mout_clkcmu_peris_noc_user", CMU_PERIS_CLK_CON_DIV_CLK_PERIS_NOCP,
+ 0, 4),
+ DIV(CLK_DOUT_PERIS_OTP, "dout_clkcmu_peris_otp",
+ "oscclk", CMU_PERIS_CLK_CON_DIV_CLK_PERIS_OTP,
+ 0, 4),
+};
+
+static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
+ /* System will hang if this critical clock is gated */
+ GATE(CLK_GOUT_CMU_PERIS, "gout_cmu_peris",
+ "dout_clkcmu_peris_nocp",
+ CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_CMU_PERIS_IPCLKPORT_PCLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_SYSREG_PERIS, "gout_sysreg_peris",
+ "dout_clkcmu_peris_nocp",
+ CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_WDT0_PERIS, "gout_wdt0_peris",
+ "dout_clkcmu_peris_nocp",
+ CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_WDT1_PERIS, "gout_wdt1_peris",
+ "dout_clkcmu_peris_nocp",
+ CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK,
+ 21, 0, 0),
+};
+
+static const unsigned long dcrg_sysreg[] __initconst = {
+ EXYNOS8855_DRCG_EN_OFFSET,
+};
+
+static const struct samsung_cmu_info peris_cmu_info __initconst = {
+ .mux_clks = peris_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(peris_mux_clks),
+ .div_clks = peris_div_clks,
+ .nr_div_clks = ARRAY_SIZE(peris_div_clks),
+ .gate_clks = peris_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
+ .nr_clk_ids = CLKS_NR_PERIS,
+ .clk_regs = peris_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
+ .sysreg_clk_regs = dcrg_sysreg,
+ .nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_sysreg),
+ .clk_name = "bus",
+ .auto_clock_gate = true,
+ .gate_dbg_offset = EXYNOS8855_PERIS_GATE_DBG_OFFSET,
+ .option_offset = CMU_PERIS_CONTROLLER_OPTION0_CMU_CTRL,
+ .drcg_offset = EXYNOS8855_DRCG_EN_OFFSET,
+};
+
static int __init exynos8855_cmu_probe(struct platform_device *pdev)
{
const struct samsung_cmu_info *info;
@@ -1109,6 +1204,9 @@ static const struct of_device_id exynos8855_cmu_of_match[] = {
{
.compatible = "samsung,exynos8855-cmu-peric",
.data = &peric_cmu_info,
+ }, {
+ .compatible = "samsung,exynos8855-cmu-peris",
+ .data = &peris_cmu_info,
}, {
.compatible = "samsung,exynos8855-cmu-top",
.data = &top_cmu_info,
--
2.34.1