[PATCH v5 0/2] arm64: errata: Add NXP iMX8QM workaround for A53 cache coherency issue

[Peng Fan (OSS)]

This picks up the work originally done by Ivan T. Ivanov in 2023 [1],
reworked to address review feedback from Will Deacon and Mark Rutland,
and rebased onto linux-next (next-20261008).

According to NXP errata document IMX8_1N94W [2], the i.MX8QuadMax and
i.MX8QuadPlus SoCs suffer from a cache coherency issue (ERR050104).
The upper bits, above bit 35, of the ARADDR and ACADDR buses within
the Arm A53 subsystem have been incorrectly connected, corrupting some
TLBI and IC maintenance operations exchanged between the A53 and A72
core clusters.

The workaround:
  - Redirects targeted TLBI operations to broadcast-all variants
    (VMALLE1IS) in the high-level TLB flush functions.
  - Upgrades IC IVAU to IC IALLUIS for both kernel and EL0 userspace.
  - Disables KVM since correct TLB maintenance cannot be guaranteed
    for guests.

Patch 1 introduces ARM64_CPUCAP_SOC_ERRATUM, a new capability type for
SoC-level errata that are probed once on the boot CPU rather than on
every CPU. This also converts ARM64_ERRATUM_4311569 to use it.

Catalin wrote the code, I just wrote the commit message, so put
Catalin as author and me as a co-developer.

Patch 2 adds the ERR050104 workaround itself.

KVM is not included in NXP software release for this platform,
so disable KVM.

There is no SOC ID SMCCC, so use DT-only approach.

Changes in v5:
- Split into two patches: preparatory ARM64_CPUCAP_SOC_ERRATUM
  infrastructure (Catalin Marinas) and the ERR050104 workaround.
- Use ARM64_CPUCAP_SOC_ERRATUM so the SoC compatible check runs only
  once on the boot CPU instead of on every CPU (Catalin Marinas).
- Drop WARN_ON(preemptible()) from is_imx8qm_soc() since it is not
  needed for a DT lookup (Catalin Marinas).
- Add T-b from Franz Schnyder
- Link to v4: https://patch.msgid.link/20260824-imx8qm-cache-coherency-v4-v4-1-b2e528c7d05e@xxxxxxx

Changes in v4:
- Rename kvm_disable_mode() to kvm_force_disabled() and place it next
  to early_kvm_mode_cfg() (Marc Zyngier).
- Also match "fsl,imx8qp" in is_imx8qm_soc() since the i.MX8QuadPlus
  is equally affected (Francesco Dolcini).
- Link to v3: https://patch.msgid.link/20260803-imx8qm-cache-coherency-v3-1-c518d0da3d3b@xxxxxxx

Changes in v3:
- Disable KVM via kvm_disable_mode() setting KVM_MODE_NONE from the
  erratum cpu_enable callback, so KVM disables itself gracefully,
  instead of a special-case check in kvm_arm_init() (Marc Zyngier).
- Link to v2: https://patch.msgid.link/20260730-imx8qm-cache-coherency-v2-1-5651aeb1af16@xxxxxxx

Changes in v2:
- Skip the workaround for local (TLBF_NOBROADCAST) TLB flushes; they
  don't cross the core's external interface (Mark Rutland).
- Preserve IC IVAU fault reporting: run "ic ivau" for the local fault
  check, then "ic ialluis" only on success (Mark Rutland).
- Link to v1: https://patch.msgid.link/20260729-imx8qm-cache-coherency-v1-1-c9864e280437@xxxxxxx

Changes from v2 [1]:
  - Moved TLBI workaround from __TLBI_1 macro to high-level flush
    functions (flush_tlb_mm, __do_flush_tlb_range, flush_tlb_kernel_range,
    __flush_tlb_kernel_pgtable) to avoid REPEAT_TLBI interaction issues,
    per Will Deacon suggestion to use static keys at the higher level.
  - Added kernel IC IVAU -> IC IALLUIS upgrade via ALTERNATIVE in
    assembler.h, per Mark Rutland review noting that only EL0 traps
    were handled in v2.
  - Added cpucap_is_possible() entry for compile-time elimination when
    CONFIG_NXP_IMX8QM_ERRATUM_ERR050104 is not set.
  - Dropped SMMU BTM changes since iMX8QM does not support broadcast TLB.

[1] https://lore.kernel.org/all/20230420112952.28340-1-iivanov@xxxxxxx/
[2] https://www.nxp.com/docs/en/errata/IMX8_1N94W.pdf

Signed-off-by: Peng Fan <peng.fan@xxxxxxx>
---
Catalin Marinas (1):
      arm64: cpufeature: add ARM64_CPUCAP_SOC_ERRATUM for SoC-level errata

Peng Fan (1):
      arm64: errata: Add NXP iMX8QM workaround for A53 cache coherency issue

 Documentation/arch/arm64/silicon-errata.rst |  2 +
 arch/arm64/Kconfig                          | 16 ++++++++
 arch/arm64/include/asm/assembler.h          |  5 +++
 arch/arm64/include/asm/cpucaps.h            |  2 +
 arch/arm64/include/asm/cpufeature.h         | 20 ++++++++++
 arch/arm64/include/asm/kvm_host.h           |  2 +
 arch/arm64/include/asm/tlbflush.h           | 62 ++++++++++++++++++-----------
 arch/arm64/kernel/cpu_errata.c              | 34 +++++++++++++++-
 arch/arm64/kernel/cpufeature.c              |  5 ++-
 arch/arm64/kernel/traps.c                   |  2 +
 arch/arm64/kvm/arm.c                        |  5 +++
 arch/arm64/tools/cpucaps                    |  1 +
 12 files changed, 130 insertions(+), 26 deletions(-)
---
base-commit: aac26bee2287c88af5be5a5ff96d783b19a28790
change-id: 20261008-imx8qm-cache-coherency-v5-831af81b406f

Best regards,
--  
Peng Fan <peng.fan@xxxxxxx>