Re: [PATCH net-next v11 03/13] dt-bindings: dpll: add SiTime SiT95316 clock generator

[Ali Rouhi]

On Mon, 5 Oct 2026, Rob Herring (Arm) wrote:

> On Wed, 30 Sep 2026 23:37:17 +0000, Ali Rouhi wrote:
> > Add a binding for the SiTime SiT9531x family of clock generators: an
> > I2C-controlled device with four independent PLLs, up to eight input
> > clocks and up to twelve outputs, described as a DPLL provider.
> >
> > [...]
>
> Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx>

Thanks for the review.  I have not carried the tag to v12, because the
binding changed there.  It is 02/12 in that series, v11 01/13 having
gone in as 45ad84d2800e.

Three named supplies were added: vdd for the PLL core, vddin for the
input receivers and dividers, and vdds for the two GPIO pins on the
SiT95317 that have a rail of their own.  The per-output VDDO pins are a
new top-level patternProperties block, with two per-variant blocks
inside the existing allOf rejecting the VDDO names the other variant
does not have.  The example gained four supply properties.  The driver
does not enable any of these; describing them gives a board with
switchable rails a way to say so.

supported-frequencies-hz on the input pins gained a description saying
the property names the rate wired to the input, as a single entry.
maxItems: 1 would say that more strongly, but dtschema types every -hz
property as a uint32 matrix, so the example's single /bits/ 64 value
reads as two cells to the tooling and the constraint fails
dt_binding_check.

Thirty-eight added lines in all, no deletions, and dt_binding_check is
clean on the result.

Thanks,
Ali