Re: [PATCH] i2c: qcom-geni: restore tSCL with 32MHz I2C fast-mode

[Sasha Levin]

> On 9/30/2026 3:01 PM, Daniel J Blueman wrote:
> > I would revert the original patch if there is hardware that uses the
> > I2C 1MHz fast-mode, since the current timings aren't to spec, but also
> > weren't before.

For stable: cb97bf3d4f91 ("i2c: qcom-geni: Fix hardcoded clock index in
SE_GENI_CLK_SEL") has already shipped in 7.2.9, 6.18.55 and 6.12.112, and is
queued for 6.6, 6.1, 5.15 and 5.10.

The 32 MHz clock map (506bb2ab0075, v6.13+) does not exist in 6.12.y and older.
The backports there pick only the 19.2 MHz entry, so the Yoga Slim 7x /
X1E80100 timing regression cannot occur on 6.12.y or older, and I'm keeping the
6.6 and older queues as they are.

7.2.y and 6.18.y do have the 32 MHz table and are affected. Once the fix lands
in mainline, I'll pick it up for 7.2 and 6.18.

-- 
Thanks,
Sasha