[PATCH v6 0/5] Add StarFive JHB100 syscon modules

[Changhuang Liang]

StarFive JHB100 has many syscon modules, as listed below:
- pcieep0_ecsr_syscon	(PCIe endpoint 0 externel syscon)
- pcieep1_ecsr_syscon
- host0_syscon		(Host0 syscon)
- host1_syscon
- husb0_syscon		(Host USB 0 syscon)
- husb1_syscon
- husbd0_syscon		(Host USB device 0 syscon)
- husbd1_syscon
- husbcmn_syscon	(Host USB common syscon)
- gpu0_syscon		(GPU0 syscon)
- gpu1_syscon
- b2h_syscon		(BMC to Host syscon)
- h2b_syscon		(Host to BMC syscon)
- vout_syscon		(Video output syscon)
- pcierp_ecsr_syscon	(PCIe root port externel syscon)
- pcierp_syscon		(PCIe root port syscon)
- usb_syscon
- npu_syscon
- per0_syscon		(Peripheral 0 syscon)
- per1_syscon
- per2_syscon
- per3_syscon
- sys0_syscon		(System 0 syscon)
- sys1_syscon
- sys2_syscon
- strap_syscon
- sfc0_filter_syscon	(SFC0 filter syscon)
- sfc1_filter_syscon
- sfc2_filter_syscon

Some syscon modules contain PLL, reset.
This series adds related drivers for PLL and reset.

This series depends on the series:
[1]: https://lore.kernel.org/all/20261008123338.11081-1-changhuang.liang@xxxxxxxxxxxxxxxx/

changes since v5:
- Remove PATCH 1/7/8 in v5

PATCH 1 (in v6):
- Split a PLL into 3 clock modules: VCO, POSTDIV, and OUT.
- Implement the PLL registration as a generic interface,
  provided for specific PLLs to call.
- Since the PLL enable/disable function is optional, the new
  version decides to remove this implementation and keep the
  PLL always on. (This may differ from the email reply in v5.)
- Remove the debugfs-related implementation.
- Add a VCO operating frequency range limit for the PLL.
- Stop recording the PLL frequency, and instead calculate it
  from the multiplier factor.

PATCH 2&3(in v6):
- Make corresponding adjustments due to the changes in PATCH 1.

PATCH 5(in v6):
Make minor adjustments due to the changes in series [1],
with no functional changes:
- select RESET_STARFIVE_COMMON ==> select RESET_STARFIVE_JH71X0

v5: https://lore.kernel.org/all/20260828095608.19955-1-changhuang.liang@xxxxxxxxxxxxxxxx/
v4: https://lore.kernel.org/all/20260809015054.210577-1-changhuang.liang@xxxxxxxxxxxxxxxx/
v3: https://lore.kernel.org/all/20260521012932.24163-1-changhuang.liang@xxxxxxxxxxxxxxxx/
v2: https://lore.kernel.org/all/20260512083521.3448-1-changhuang.liang@xxxxxxxxxxxxxxxx/
V1: https://lore.kernel.org/all/20260403054945.467700-1-changhuang.liang@xxxxxxxxxxxxxxxx/

Changhuang Liang (5):
  clk: starfive: Add system-0 domain PLL clock driver
  clk: starfive: Add Peripheral-0 domain PLL clock driver
  clk: starfive: Add Peripheral-1 domain PLL clock driver
  reset: starfive: Introduce active_low
  reset: starfive: Add syscon reset driver support

 drivers/clk/starfive/Kconfig                  |  28 ++
 drivers/clk/starfive/Makefile                 |   3 +
 .../starfive/clk-starfive-jhb100-per-pll.c    |  95 ++++
 .../clk/starfive/clk-starfive-jhb100-pll.c    | 425 ++++++++++++++++++
 .../clk/starfive/clk-starfive-jhb100-pll.h    |  63 +++
 .../starfive/clk-starfive-jhb100-sys0-pll.c   |  69 +++
 drivers/reset/starfive/Kconfig                |   9 +
 drivers/reset/starfive/Makefile               |   1 +
 .../reset/starfive/reset-starfive-jh71x0.c    |   3 +-
 .../reset/starfive/reset-starfive-jh71x0.h    |   6 +
 .../starfive/reset-starfive-jhb100-syscon.c   |  61 +++
 11 files changed, 762 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per-pll.c
 create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-pll.c
 create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-pll.h
 create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys0-pll.c
 create mode 100644 drivers/reset/starfive/reset-starfive-jhb100-syscon.c

--
2.25.1