Re: [PATCH 2/2] arm64: Apply existing Apple CPU workarounds to M3 and M4

[Marc Zyngier]

On Sat, 10 Oct 2026 11:54:16 +0100,
Myria Sarvay <myrialsarvay@xxxxxxxxx> wrote:
> 
> Hi Marc,
> 
> (Resending because I forgot to reply all, sorry Marc)
> 
> On Fri, Oct 09, 2026 at 09:16:03AM +0100, Marc Zyngier wrote:
> > On Fri, 09 Oct 2026 01:03:57 +0100,
> > Michael Reeves <michael.reeves077@xxxxxxxxx> wrote:
> > > 
> > > > I can provide the binary (and a few scripts) to test this easily.
> > > > Should they have been fixed, we can always create a second
> > > > implementation list to cover the PMU.
> > > 
> > > Can you please send that so we can try? That would be much
> > > appreciated, thank you.
> > 
> > I've sent you (and Yureka) details over IRC. If you need help with
> > setting things up, let me know directly.
> > 
> > Thanks,
> > 
> > 	M.
> > 
> > -- 
> > Without deviation from the norm, progress is not possible.
> 
> I've tested the patches on my M3 Max (t6031-j514c), and without these
> patches, it SErrors, and with them (and including the M3/M4 MIDRs in
> the has_vgic_v3 list in arch/arm64/kernel/cpufeature.c) it doesn't
> SError, and the iso boots correctly to a login getty.

Thanks for letting me know.

When you post v2 to fix the has_vgic_v3 list, please collect the
details of what this was tested on in the cover letter, it may become
useful in the future.

Cheers,

	M.

-- 
Without deviation from the norm, progress is not possible.