Re: [PATCH] sparc64: Use relaxed ordering for DMA_FROM_DEVICE mappings on sun4v

[Leon Romanovsky]

On Tue, Oct 13, 2026 at 03:37:30PM +0200, Stian Halseth wrote:
> sun4v IOMMU and ATU mappings carry a relaxed ordering attribute, but
> dma_4v_map_phys() and dma_4v_map_sg() set it only when the caller
> passes DMA_ATTR_WEAK_ORDERING. Some network drivers do, storage drivers
> do not. Without it every device write into memory is strictly ordered,
> which on a T7-1 (M7) caps DMA reads at about 280 MiB/s per PCIe device
> while writes run at full speed.
> 
> Set the attribute for every DMA_FROM_DEVICE streaming mapping. Devices
> report completion through coherent memory or an interrupt, which stay
> strictly ordered, and a strictly ordered write does not pass the writes
> before it.
> 
> T7-1, fio 1M sequential read, QD32:
> 
>                       before        after
>   NVMe (PM1725, x4)   281 MiB/s     3169 MiB/s
>   SATA SSD (mpt3sas)  278 MiB/s      502 MiB/s
> 
> Closes: https://github.com/sparclinux/issues/issues/114
> Signed-off-by: Stian Halseth <stian@xxxxxx>
> ---
> Tested on a T7-1 (M7) and a T4-1:
> 
> - T7: fresh RAID1 on two NVMe drives, 192 GB fio crc32c write+verify
>   and md check: no errors, mismatch_cnt 0.
> - T7 and T4: file checksums on the SAS boot mirrors identical to a
>   strictly ordered kernel; no new messages in dmesg.
> - 4k random read and sequential writes unchanged.
> 
>  arch/sparc/kernel/pci_sun4v.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 

Looks right to me.

Thanks,
Reviewed-by: Leon Romanovsky <leon@xxxxxxxxxx>