Re: [PATCH v5 0/2] riscv: kprobes: reject probes inside LR/SC sequences

[Google]

On Wed, 14 Oct 2026 17:44:13 +0800, Xiaofeng Yuan <yuanxiaofeng@xxxxxxxxxxxxxxxxxx> wrote:
> A breakpoint trap taken in the middle of an LR/SC sequence clears the
> load reservation, so an SC following the probed instruction always fails
> and the enclosing retry loop re-enters the breakpoint, livelocking the
> CPU.  This series makes the RISC-V kprobes implementation reject probes
> placed on an LR/SC instruction or between them, following arm64's
> approach for its equivalent exclusive load/store instructions.
>

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Thanks,

-- 
Masami Hiramatsu (Google) <mhiramat@xxxxxxxxxx>