Re: [PATCH net-next v13 02/12] dt-bindings: dpll: add SiTime SiT95316 clock generator

[Ali Rouhi]

On Wed, 14 Oct 2026, Rob Herring wrote:
> > +                   supported-frequencies-hz = /bits/ 64 <10000000>;
>
> -hz is 32-bit.

Fixed in v14: the examples give the rates as 32-bit cells and the
driver reads the property with the u32 helpers.  Every rate the part
accepts fits in 32 bits.

With the width right, the input pins' list also takes the maxItems: 1
that its single-entry description had promised, which the Sashiko
review asked for on the same patch.  At 64 bits each rate decoded as
two cells and the constraint failed on the example itself.

Separate from this patch: microchip,zl30731.yaml writes the same
property /bits/ 64 in its examples and zl3073x reads it with
fwnode_property_read_u64_array().  dpll-pin.yaml gives the property no
type, so the -hz default applies there as well, and those examples
encode each rate as two cells.

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